- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380227 > CYV15G0404DXB-BGC (CYPRESS SEMICONDUCTOR CORP) Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker PDF資料下載
參數(shù)資料
| 型號： | CYV15G0404DXB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 11/43頁 |
| 文件大?。?/td> | 814K |
| 代理商： | CYV15G0404DXB-BGC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 11 of 43
LFIA
LFIB
LFIC
LFID
LVTTL Output,
asynchronous
Link Fault Indication Output
. LFIx is an output status indicator signal. LFIx is the
logical OR of five internal conditions. LFIx is asserted LOW when any of the
following conditions is true:
Received serial data rate outside expected range
Analog amplitude below expected levels
Transition density lower than expected
Receive channel disabled
ULCx is LOW
Absence of REFCLKx±.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Write Enable
. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.
[5]
Control Addressing Bus
. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[7:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.
[5]
Table 9
lists
the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET.
Table 10
shows how the latches are
mapped in the device.
Control Data Bus
. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
[5 ]
Table 9
lists the configu-
ration latches within the device, and the initialization value of the latches upon the
assertion of RESET.
Table 10
shows how the latches are mapped in the device.
DATA[7:0]
LVTTL input
asynchronous,
internal pull-up
Internal Device Configuration Latches
RFMODE[A..D][1:0]
FRAMCHAR[A..D]
DECMODE[A..D]
DECBYP[A..D]
RXCKSEL[A..D]
RXRATE[A..D]
SDASEL[A..D][1:0]
ENCBYP[A..D]
TXCKSEL[A..D]
TXRATE[A..D]
RFEN[A..D]
RXPLLPD[A..D]
RXBIST[A..D]
TXBIST[A..D]
OE2[A..D]
OE1[A..D]
PABRST[A..D]
GLEN[11..0]
FGLEN[2..0]
Factory Test Modes
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Reframe Mode Select
.
Framing Character Select
.
Receiver Decoder Mode Select
.
Receiver Decoder Bypass
.
Receive Clock Select
.
Receive Clock Rate Select
.
Signal Detect Amplitude Select
.
Transmit Encoder Bypassed
.
Transmit Clock Select
.
Transmit PLL Clock Rate Select
.
Reframe Enable
.
Receive Channel Power Control
.
Receive Bist Disabled
.
Transmit Bist Disabled
.
Differential Serial Output Driver 2 Enable
.
Differential Serial Output Driver 1 Enable
.
Transmit Clock Phase Alignment Buffer Reset
.
Global Latch Enable
.
Force Global Latch Enable
.
Note:
6.
See
Device Configuration and Control Interface
for detailed information on the internal latches.
Pin Definitions
(continued)
CYV15G0404DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0404DXB-BGI | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| CYW15G0201DXB | Dual-channel HOTLink II Transceiver(雙通道HOTLink II收發(fā)器) |
| CYW15G0401DXB | Quad HOTLink II Transceiver(四熱連接II收發(fā)器) |
| CYW2330 | Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers |
| CYW2331 | Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0404DXB-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| CYV15G0404DXB-BGXC | 功能描述:電信線路管理 IC 3.3V QUAD HOTLINK II TRANS W/RECLOCKER RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0404DX-EVAL | 功能描述:界面開發(fā)工具 Quad Indep Ch HOTLink II XCVR RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYV15G0404RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。