參數(shù)資料
型號: CYV15G0404DXB-BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA256
封裝: 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256
文件頁數(shù): 10/43頁
文件大?。?/td> 814K
代理商: CYV15G0404DXB-BGC
PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 10 of 43
LDTDEN
LVTTL Input,
internal pull-up
Level Detect Transition Density Enable
. When LDTDEN is HIGH, the Signal
Level Detector, Range Controller, and Transition Density Detector are all enabled
to determine if the RXPLL tracks REFCLKx± or the selected input serial data
stream. If the Signal Level Detector, Range Controller, or Transition Density
Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks
to REFCLK± until such a time they become valid. The (SDASEL[A..D][1:0]) are
used to configure the trip level of the Signal Level Detector. The Transition Density
Detector limit is one transition in every 60 consecutive bits. When LDTDEN is
LOW, only the Range Controller is used to determine if the RXPLL tracks
REFCLKx± or the selected input serial data stream. For the cases when
RXCKSELx = 0 (recovered clock), it is recommended to set LDTDEN = HIGH.
Reclocker Enable
. When RCLKENx is HIGH, the RXPLL performs Clock and
Data Recovery functions on the input serial data stream and routes the deseri-
alized data to the RXDx[7:0] and RXSTA[2:0] parallel data outputs as configured
by DECBYPx, as well as presenting the reclocked serial data to the enabled Differ-
ential Serial Outputs.
When RCLKENx is LOW, the receive reclocker is disabled and the TXDx[7:0]
parallel data inputs and TXCTx[1:0] inputs are interpreted (as configured by
ENCBYPx) to generate appropriate 10-bit characters that are presented to the
Differential Serial Outputs.
The reclocker feature is optimized to be used for SMPTE video applications.
Use Local Clock
. When ULCx is LOW, the RXPLL is forced to lock to REFCLKx±
instead of the received serial data stream. While ULCx is LOW, the LFIx for the
associated channel is LOW indicating a link fault.
When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on
the input data streams. This function is used in applications in which a stable
RXCLKx± is needed. In cases when there is an absence of valid data transitions
for a long period of time, or the high-gain differential serial inputs (INx±) are left
floating, there may be brief frequency excursions of the RXCLKx± outputs from
REFCLKx±.
Serial Rate Select
. The SPDSELx inputs specify the operating signaling-rate
range of each channel’s transmit and receive PLL.
LOW = 195 – 400 MBd
MID = 400 – 800 MBd
HIGH = 800 – 1500 MBd.
Receive Input Selector
. The INSELx input determines which external serial bit
stream is passed to the receiver’s Clock and Data Recovery circuit. When INSELx
is HIGH, the Primary Differential Serial Data Input, INx1±, is selected for the
associated receive channel. When INSELx is LOW, the Secondary Differential
Serial Data Input, INx2±, is selected for the associated receive channel.
Loop-Back-Enable
. The LPENx input enables the internal serial loop-back for the
associated channel. When LPENx is HIGH, the transmit serial data from the
associated channel is internally routed to the associated receive Clock and Data
Recovery (CDR) circuit. All enabled serial drivers on the channel are forced to
differential logic-1, and the serial data inputs are ignored. When LPENx is LOW,
the internal serial loop-back function is disabled.
RCLKENA
RCLKENB
RCLKENC
RCLKEND
LVTTL Input,
internal pull-down
ULCA
ULCB
ULCC
ULCD
LVTTL Input,
internal pull-up
SPDSELA
SPDSELB
SPDSELC
SPDSELD
3-Level Select
[4]
static control input
INSELA
INSELB
INSELC
INSELD
LVTTL Input,
asynchronous
LPENA
LPENB
LPENC
LPEND
LVTTL Input,
asynchronous,
internal pull-down
Notes:
4.
3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
See
Device Configuration and Control Interface
for detailed information on the operation of the Configuration Interface.
5.
Pin Definitions
(continued)
CYV15G0404DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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