參數(shù)資料
型號(hào)： CYV15G0404DXB-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256
文件頁(yè)數(shù)： 20/43頁(yè)
文件大?。?/td> 814K
代理商： CYV15G0404DXB-BGC
PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 20 of 43
cation's lifetime.The first row of latches for each channel
(address numbers 0, 3, 7, and 10) are the static receiver
control latches. The second row of latches for each channel
(address numbers 1, 4, 8, and 11) are the static transmitter
control latches. The third row of latches for each channel
(address numbers 2, 5, 9, and 12) are the dynamic control
latches that are associated with enabling dynamic functions
within the device.
Latch Bank 14 is also useful for those users that do not need
the latch-based programmable feature of the device. This
latch bank could be used in those applications that do not need
to modify the default value of the static latch banks, and that
can afford a global (i.e., not independent) control of the
dynamic signals. In this case, this feature becomes available
when ADDR[3:0] is left unchanged with a value of “1110” and
WREN is left asserted. The signals present in DATA[7:0] effec-
tively become global control pins, and for the latch banks 2, 5,
8 and 11.
Table 9. Device Configuration and Control Latch Descriptions
Name
RFMODEA[1:0]
RFMODEB[1:0]
RFMODEC[1:0]
RFMODED[1:0]
Signal Description
Reframe Mode Select
. The initialization value of the RFMODEx [1:0] latches = 10. RFMODEx is used
to select the operating mode of the framer. When RFMODEx[1:0] = 00, the low-latency framer is
selected. This frames on each occurrence of the selected framing character(s) in the received data
stream. This mode of framing stretches the recovered clock for one or multiple cycles to align that clock
with the recovered data. When RFMODEx[1:0] = 01, the alternate mode Multi-Byte parallel framer is
selected. This requires detection of the selected framing character(s) in the received serial bit stream,
on identical 10-bit boundaries, on four directly adjacent characters. The recovered character clock
remains in the same phasing regardless of character offset. When RFMODEx[1:0] =10, the Cypress-
mode Multi-Byte parallel framer is selected. This requires a pair of the selected framing character(s), on
identical 10-bit boundaries, within a span of 50 bits, before the character boundaries are adjusted. The
recovered character clock remains in the same phasing regardless of character offset. RFMODEx[1:0]
= 11 is reserved for test.
Framing Character Select
. The initialization value of the FRAMCHARx latch = 1. FRAMCHARx is used
to select the character or portion of a character used for framing of each channel’s received data stream.
When FRAMCHARx = 1, the framer looks for either disparity of the K28.5 character. When FRAMCHARx
= 0, the framer looks for either disparity of the 8-bit Comma characters. The specific bit combinations of
these framing characters are listed in
Table 6
.
Receiver Decoder Mode Select
. The initialization value of the DECMODEx latch = 1. DECMODEx
selects the Decoder Mode used for the associated channel. When DECMODEx = 1 and decoder is
enabled, the Cypress Decoding Mode is used. When DECMODEx = 0 and decoder is enabled, the
Alternate Decoding mode is used. When the decoder is enabled (DECBYPx = 1), the 10-bit transmission
characters are decoded using
Table 15
and
Table 16
. The column used in the Special Characters
Table 16
is determined by the DECMODEx latch.
Receiver Decoder Bypass
. The initialization value of the DECBYPx latch = 1. DECBYPx selects if the
Receiver Decoder is enabled or bypassed. When DECBYPx = 1, the decoder is enabled and the Decoder
Mode is selected by DECMODEx. When DECBYPx = 0 and DECMODEx = 1, the decoder is bypassed
and raw 10-bit characters are passed through the receiver.
Receive Clock Select
. The initialization value of the RXCKSELx latch = 1.
RXCKSELx selects the
receive clock source used to transfer data to the Output Registers and the clock source for the RXCLK
±
output. When RXCKSELx = 1, the associated Output Registers
,
are clocked by REFCLKx± at the
associated RXCLKx
±
output buffer. When RXCKSELx = 0, the associated Output Registers, are clocked
by the Recovered Byte clock at the associated RXCLKx
±
output buffer. These output clocks may operate
at the character-rate or half the character-rate as selected by RXRATEx.
FRAMCHARA
FRAMCHARB
FRAMCHARC
FRAMCHARD
DECMODEA
DECMODEB
DECMODEC
DECMODED
DECBYPA
DECBYPB
DECBYPC
DECBYPD
RXCKSELA
RXCKSELB
RXCKSELC
RXCKSELD
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