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參數(shù)資料
| 型號： | CYV15G0404DXB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 28/43頁 |
| 文件大小： | 814K |
| 代理商： | CYV15G0404DXB-BGC |
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PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 28 of 43
CYV15G0404DXB AC Electrical Characteristics
Parameter
CYV15G0404DXB Transmitter LVTTL Switching Characteristics
Over the Operating Range
f
TS
TXCLKx Clock Cycle Frequency
t
TXCLK
TXCLKx Period=1/f
TS
t
TXCLKH[20]
TXCLKx HIGH Time
t
TXCLKL[20]
TXCLKx LOW Time
t
TXCLKR [20, 21, 22]
TXCLKx Rise Time
t
TXCLKF [20, 21, 22]
TXCLKx Fall Time
t
TXDS
Transmit Data Set-up Time to
TXCLKx
↑
(TXCKSELx
≠
0)
t
TXDH
Transmit Data Hold Time from TXCLKx
↑
(TXCKSELx
≠
0)
f
TOS
TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency
t
TXCLKO
TXCLKOx Period=1/f
TOS
t
TXCLKOD
TXCLKO Duty Cycle centered at 60% HIGH time
CYV15G0404DXB Receiver LVTTL Switching Characteristics
Over the Operating Range
f
RS
RXCLKx± Clock Output Frequency
t
RXCLKP
RXCLKx± Period = 1/f
RS
t
RXCLKD
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate when
RXCKSELx = 0)
t
RXCLKR [20]
RXCLKx± Rise Time
t
RXCLKF [20]
RXCLKx± Fall Time
t
RXDv–[23]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0, RXCKSELx = 0)
(Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1, RXCKSELx = 0)
(Half Rate)
t
RXDv+[23]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0, RXCKSELx = 0)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1, RXCKSELx =0)
CYV15G0404DXB REFCLKx Switching Characteristics
Over the Operating Range
f
REF
REFCLKx Clock Frequency
t
REFCLK
REFCLKx Period = 1/f
REF
t
REFH
REFCLKx HIGH Time (TXRATEx = 1)(Half Rate)
REFCLKx HIGH Time (TXRATEx = 0)(Full Rate)
t
REFL
REFCLKx LOW Time (TXRATEx = 1)(Half Rate)
REFCLKx LOW Time (TXRATEx = 0)(Full Rate)
t
REFD[25]
REFCLKx Duty Cycle
t
REFR [20, 21, 22]
REFCLKx Rise Time (20%–80%)
t
REFF[20, 21, 22]
REFCLKx Fall Time (20%–80%)
t
TREFDS
Transmit Data Set-up Time to
REFCLKx (TXCKSELx
=
1)
Notes:
15. The common mode range defines the allowable range of INPUT+ and INPUT
when INPUT+ = INPUT
. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
16. Maximum I
is measured with V
CC
= MAX, RFENx = 0,T
A
= 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01
pattern, and outputs unloaded.
17. Typical I
is measured under similar conditions except with V
= 3.3V, T
= 25°C, RFENx = 0, with all channels enabled and one Serial Line Driver per
transmit channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
18. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
19. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
20. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
21. The ratio of rise time to falling time must not vary by greater than 2:1.
22. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
23. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
24. Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when TXRATEx = 1) or 1/(f
REF
* 10) (when TXRATEx = 0). In an operating link this is equivalent to t
.
25. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLKx± duty
cycle cannot be as large as 30%–70%.
Description
Min.
Max
Unit
19.5
6.66
2.2
2.2
0.2
0.2
1.7
0.8
19.5
6.66
-1
150
51.28
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
1.7
1.7
150
51.28
0
9.75
6.66
–1.0
150
102.56
+1.0
MHz
ns
ns
0.3
0.3
1.2
1.2
ns
ns
ns
5UI–1.5
[24]
5UI–1.0
[24]
ns
5UI–1.8
[24]
5UI–2.3
[24]
ns
ns
19.5
6.6
5.9
2.9
[20]
5.9
2.9
[20]
30
150
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
ns
70
2
2
1.7
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|---|---|
| CYV15G0404DXB-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
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| CYV15G0404RB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
| CYV15G0404RB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
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