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參數(shù)資料
| 型號： | CYRF69213-40LFXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, M0-220, QFN-40 |
| 文件頁數(shù)： | 66/85頁 |
| 文件大小： | 731K |
| 代理商： | CYRF69213-40LFXC |
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CYRF69213
Document #: 001-07552 Rev. *B
Page 66 of 85
Mnemonic
XACT_CFG_ADR
Address
0x0F
Bit
7
6
5
4
3
2
1
0
Default
1
-
0
0
0
0
0
0
Read/Write
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
Function
ACK EN
Not Used
FRC END
END STATE
ACK TO
Bit 7
Acknowledge Enable. When this bit is set, an ACK packet is automatically transmitted whenever a valid packet is received; in
this case the device is considered to be in transaction mode. After transmission of the ACK packet, the device automatically
transitions to the END STATE. When this bit is cleared, the device transitions directly to the END STATE immediately after the
end of packet transmission.
Force End State. Setting this bit forces a transition to the state set in END STATE. By setting the desired END STATE at the
same time as setting this bit the device may be forced to immediately transition from its current state to any other state. This bit
is automatically cleared upon completion.
Transaction End State. This field defines the mode to which the device transitions after receiving or transmitting a packet. 000
= Sleep Mode; 001 = Idle Mode; 010 = Synth Mode (TX); 011 = Synth Mode (RX); 100 = RX Mode. In normal use, this field will
typically be set to 000 or 001 when the device is transmitting packets and 100 when the device is receiving packets. Note that
when the device transitions to receive mode as an END STATE, the receiver must still be armed by setting RX GO before the
device can begin receiving data. If the system only support packets <=16 bytes then firmware should examine RXC IRQ and
RXE IRQ to determine the status of the packet. If the system supports packets > 16 bytes ensure that END STATE is not sleep,
force RXF = 1, perform receive operation, force RXF = 0, and if necessary set END STATE back to sleep.
ACK Timeout. When the device is configured for transaction mode, this field sets the timeout period after transmission of a
packet during which an ACK must be correctly received in order to prevent a transmit error condition from being detected. This
timeout period is expressed in terms of a number of SOP_CODE_ADR code lengths; if SOP LEN is set, then the timeout period
is this value multiplied by 64
μ
s and if SOP LEN is cleared then the timeout is this value multiplied by 32
μ
s. 00 = 4x, 01 = 8x,
10 = 12x, 11 = 15x the SOP_CODE_ADR code length. ACK_TO must be set to greater than 30 + Data Code Length (only for
8DR) + Preamble Length + SOP Code Length (x2).
Bit 5
Bits 4:2
Bits 1:0
Mnemonic
FRAMING_CFG_ADR
Address
0x10
Bit
7
6
5
4
3
2
1
0
Default
1
0
1
0
0
1
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SOP EN
SOP LEN
LEN EN
SOP TH
Bit 7
SOP Enable. When this bit is set, each transmitted packet begins with a SOP field, and only packets beginning with a valid
SOP field will be received. If this bit is cleared, no SOP field will be generated when a packet is transmitted, and packet recep-
tion will begin whenever two successive correlations against the DATA_CODE_ADR code are detected.
SOP PN Code Length. When this bit is set the SOP_CODE_ADR code length is 64 chips. When this bit is cleared the
SOP_CODE_ADR code length is 32 chips.
Packet Length Enable. When this bit is set the 8-bit value contained in TX_LENGTH_ADR is transmitted immediately after the
SOP field. In receive mode, the 8 bits immediately following the SOP field are interpreted as the length of the packet. When this
bit is cleared no packet length field is transmitted. 8DR always sends the packet length field (forces LEN EN = 1). GFSK
requires user set LEN EN = 1.
SOP Correlator Threshold. This is the receive data correlator threshold used when attempting to detect a SOP symbol. There
is a threshold for the SOP_CODE_ADR code. This (single) threshold is applied independently to each of SOP1 and SOP2
fields. There are then two thresholds for each of the 64-chip DATA_CODE_ADR codes and 32-chip DATA_CODE_ADR codes.
When SOP LEN is set, all 5 bits of this field are used. When SOP LEN is cleared, the most significant bit is disregarded. Typical
applications configure SOP TH = 04h for SOP32 and SOP TH = 0Eh for SOP64.
Bit 6
Bit 5
Bits 4:0
[+] Feedback
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69213-40LTXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CYRF69213A-40LFXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| CYRF69213A-40LTXC | 功能描述:射頻收發(fā)器 CYRF69213A-40LTXC RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| CYRF69303 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio-on-Chip LPstar |
| CYRF69303-40LFXC | 功能描述:射頻微控制器 - MCU M8C 8bit 2.4GHz 8KB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:Si100x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:24 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LGA-42 安裝風格:SMD/SMT 封裝:Tube |
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