參數(shù)資料
型號: CYRF69213-40LFXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Programmable Radio on Chip Low Power
中文描述: SPECIALTY TELECOM CIRCUIT, QCC40
封裝: 6 X 6 MM, LEAD FREE, M0-220, QFN-40
文件頁數(shù): 25/85頁
文件大?。?/td> 731K
代理商: CYRF69213-40LFXC
CYRF69213
Document #: 001-07552 Rev. *B
Page 25 of 85
Table 35.USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Read/Write
Default
This register is used to trim the Internal 24-MHz Oscillator using received low-speed USB packets as a timing reference. The USB Osclock
circuit is active when the Internal 24-MHz Oscillator provides the USB clock
Bits 7:2
Reserved
Bit 1
Fine Tune Only
0 = Enable
1 = Disable the oscillator lock from performing the course-tune portion of its retuning. The oscillator lock must be allowed to per-
form a course tuning in order to tune the oscillator for correct USB SIE operation. After the oscillator is properly tuned this bit can
be set to reduce variance in the internal oscillator frequency that would be caused by course tuning
Bit 0
USB Osclock Disable
0 = Enable. With the presence of USB traffic, the Internal 24-MHz Oscillator precisely tunes to 24 MHz ± 1.5%
1 = Disable. The Internal 24-MHz Oscillator is not trimmed based on USB packets. This setting is useful when the internal oscil-
lator is not sourcing the USBSIE clock
Reserved
Fine Tune
Only
R/W
0
USB Osclock
Disable
R/W
0
0
0
0
0
0
0
Table 36.Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Bit #
Field
Read/Write
Default
Bits 7:6
7
TCAPCL Divider
R/W
-
TCAPCLK Divider
TCAPCLK Divider controls the TCAPCLK divisor
00 = Divide by 2
01 = Divide by 4
10 = Divide by 6
11 = Divide by 8
TCAPCLK Select
The TCAPCLK Select field controls the source of the TCAPCLK
0 0 = Internal 24-MHz Oscillator
0 1 = External crystal oscillator—external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled,
CLKIN input if the external crystal oscillator is disabled (the XOSC Enable bit of the CLKIOCR Register is cleared—
Table 37
)
1 0 = Internal 32-KHz Low-power Oscillator
1 1 = TCAPCLK Disabled
Note
The 1024-
μ
s interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency will cause a
corresponding change in the 1024-
μ
s interval timer frequency
Bits 3:2
ITMRCLK Divider
ITMRCLK Divider controls the ITMRCLK divisor.
0 0 = Divider value of 1
0 1 = Divider value of 2
1 0 = Divider value of 3
1 1 = Divider value of 4
Bits 1:0
ITMRCLK Select
0 0 = Internal 24-MHz Oscillator
0 1 = External crystal oscillator – external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled,
CLKIN input if the external crystal oscillator is disabled
1 0 = Internal 32-KHz Low-power Oscillator
1 1 = TCAPCLK
6
5
TCAPCLK Select
R/W
-
4
3
ITMRCLK Divider
R/W
1
2
1
ITMRCLK Select
R/W
0
0
R/W
-
R/W
-
R/W
1
R/W
0
Bits 5:4
[+] Feedback
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