參數(shù)資料
型號(hào)： CYRF69213-40LFXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Programmable Radio on Chip Low Power
中文描述： SPECIALTY TELECOM CIRCUIT, QCC40
封裝： 6 X 6 MM, LEAD FREE, M0-220, QFN-40
文件頁(yè)數(shù)： 45/85頁(yè)
文件大?。?/td> 731K
代理商： CYRF69213-40LFXC
CYRF69213
Document #: 001-07552 Rev. *B
Page 45 of 85
Interrupt Processing
The sequence of events that occur during interrupt processing
is as follows:
1. An interrupt becomes active, either because:
a. The interrupt condition occurs (for example, a timer
expires).
b. A previously posted interrupt is enabled through an
update of an interrupt mask register.
c. An interrupt is pending and GIE is set from 0 to 1 in the
CPU Flag register.
2. The current executing instruction finishes.
3. The internal interrupt is dispatched, taking 13 cycles. During
this time, the following actions occur:
a. The MSB and LSB of Program Counter and Flag
registers (CPU_PC and CPU_F) are stored onto the
program stack by an automatic CALL instruction (13
cycles) generated during the interrupt acknowledge
process.
b. The PCH, PCL, and Flag register (CPU_F) are stored
onto the program stack (in that order) by an automatic
CALL instruction (13 cycles) generated during the
interrupt acknowledge process.
c. The CPU_F register is then cleared. Since this clears the
GIE bit to 0, additional interrupts are temporarily
disabled
d. The PCH (PC[15:8]) is cleared to zero.
e. The interrupt vector is read from the interrupt controller
and its value placed into PCL (PC[7:0]). This sets the
program counter to point to the appropriate address in
the interrupt table (for example, 0004h for the POR/LVD
interrupt).
4. Program execution vectors to the interrupt table. Typically,
a LJMP instruction in the interrupt table sends execution to
the user's Interrupt Service Routine (ISR) for this interrupt.
5. The ISR executes. Note that interrupts are disabled since
GIE = 0. In the ISR, interrupts can be re-enabled if desired
by setting GIE = 1 (care must be taken to avoid stack
overflow).
6. The ISR ends with a RETI instruction which restores the
Program Counter and Flag registers (CPU_PC and
CPU_F). The restored Flag register re-enables interrupts,
since GIE = 1 again.
7. Execution resumes at the next instruction, after the one that
occurred before the interrupt. However, if there are more
pending interrupts, the subsequent interrupts will be
processed before the next normal program instruction.
Interrupt Latency
The time between the assertion of an enabled interrupt and the
start of its ISR can be calculated from the following equation.
Latency = Time for current instruction to finish + Time for
internal interrupt routine to execute + Time for LJMP
instruction in interrupt table to execute.
For example, if the 5-cycle JMP instruction is executing when
an interrupt becomes active, the total number of CPU clock
cycles before the ISR begins would be as follows:
(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt
routine) + (7 cycles for LJMP) = 21 to 25 cycles.
In the example above, at 24 MHz, 25 clock cycles take
1.042
μ
s.
Interrupt Registers
The Interrupt Registers are discussed it the following sections.
Interrupt Clear Register
The Interrupt Clear Registers (INT_CLRx) are used to enable
the individual interrupt sources’ ability to clear posted inter-
rupts.
When an INT_CLRx register is read, any bits that are set
indicates an interrupt has been posted for that hardware
resource. Therefore, reading these registers gives the user the
ability to determine all posted interrupts.
Table 66. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]
Bit #
Field
Read/Write
Default
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT (Bit 7 of the
INT_MSK3 Register) will post the corresponding hardware interrupt
7
6
5
4
3
2
1
0
GPIO Port 1
R/W
0
Sleep Timer
R/W
0
INT1
R/W
0
GPIO Port 0
R/W
0
SPI Receive
R/W
0
SPI Transmit
R/W
0
INT0
R/W
0
POR/LVD
R/W
0
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CYRF69213-40LTXC 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CYRF69213A-40LFXC 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CYRF69213A-40LTXC 功能描述:射頻收發(fā)器 CYRF69213A-40LTXC RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類(lèi)型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類(lèi)型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
CYRF69303 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Programmable Radio-on-Chip LPstar
CYRF69303-40LFXC 功能描述:射頻微控制器 - MCU M8C 8bit 2.4GHz 8KB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:Si100x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LGA-42 安裝風(fēng)格:SMD/SMT 封裝:Tube
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