參數(shù)資料
型號(hào)： CYRF69213-40LFXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Radio on Chip Low Power
中文描述： SPECIALTY TELECOM CIRCUIT, QCC40
封裝： 6 X 6 MM, LEAD FREE, M0-220, QFN-40
文件頁數(shù)： 30/85頁
文件大小： 731K
代理商： CYRF69213-40LFXC
CYRF69213
Document #: 001-07552 Rev. *B
Page 30 of 85
Figure 12. Sleep Timing
Wakeup Sequence
Once asleep, the only event that can wake the system up is
an interrupt. The global interrupt enable of the CPU flag
register does not need to be set. Any unmasked interrupt will
wake the system up. It is optional for the CPU to actually take
the interrupt after the wakeup sequence. The wakeup
sequence is synchronized to the 32-KHz clock for purposes of
sequencing a startup delay, to allow the Flash memory module
enough time to power up before the CPU asserts the first read
access. Another reason for the delay is to allow the oscillator,
Bandgap, and LVD/POR circuits time to settle before actually
being used in the system. As shown in
Figure 13
, the wakeup
sequence is as follows:
1. The wakeup interrupt occurs and is synchronized by the
negative edge of the 32-KHz clock.
2. At the following positive edge of the 32-KHz clock, the
system-wide PD signal is negated. The Flash memory
module, internal oscillator, EFTB, and bandgap circuit are
all powered up to a normal operating state.
3. At the following positive edge of the 32-KHz clock, the
current values for the precision POR and LVD have settled
and are sampled.
4. At the following negative edge of the 32-KHz clock (after
about 15 μs nominal), the BRQ signal is negated by the
sleep logic circuit. On the following CPUCLK, BRA is
negated by the CPU and instruction execution resumes.
Note that in
Figure 13
fixed function blocks, such as Flash,
internal oscillator, EFTB, and bandgap, have about 15 μs
start up. The wakeup times (interrupt to CPU operational)
will range from 75 μs to 105 μs.
Firmware write to SCR
SLEEP bit causes an
immediate BRQ
IOW
SLEEP
BRQ
PD
BRA
CPUCLK
CPU captures
BRQ on next
CPUCLK edge
CPU
responds
with a BRA
On the falling edge of
CPUCLK, PD is asserted.
The 24/48 MHz system clock
is halted; the Flash and
bandgap are powered down
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYRF69213-40LTXC 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CYRF69213A-40LFXC 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
CYRF69213A-40LTXC 功能描述:射頻收發(fā)器 CYRF69213A-40LTXC RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
CYRF69303 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio-on-Chip LPstar
CYRF69303-40LFXC 功能描述:射頻微控制器 - MCU M8C 8bit 2.4GHz 8KB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:Si100x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LGA-42 安裝風(fēng)格:SMD/SMT 封裝:Tube
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