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參數(shù)資料
| 型號(hào)： | CYRF69213-40LFXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, M0-220, QFN-40 |
| 文件頁(yè)數(shù)： | 5/85頁(yè) |
| 文件大?。?/td> | 731K |
| 代理商： | CYRF69213-40LFXC |
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CYRF69213
Document #: 001-07552 Rev. *B
Page 5 of 85
Functional Block Overview
All the blocks that make up the PRoC LP are presented here.
2.4-GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in 7 steps. The supply current of the
device is reduced as the RF output power is reduced.
Frequency Synthesizer
Before transmission or reception may commence, it is
necessary for the frequency synthesizer to settle. The settling
time varies depending on channel; 25 fast channels are
provided with a maximum settling time of 100
μ
s.
The ‘fast channels’ (<100-
μ
s settling time) are every third
frequency, starting at 2400 MHz up to and including 2472 MHz
(for example, 0,3,6,9…….69 & 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16
generation and checking, as well as EOP detection and length
field.
Data Rates and Data Transmission Modes
The SoC supports four different data transmission modes:
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
In 8DR mode, 8 bits are encoded in each
DATA_CODE_ADR derived code symbol transmitted.
In DDR mode, 2-bits are encoded in each
DATA_CODE_ADR derived code symbol transmitted. (As
in the CYWUSB6934 DDR mode).
In SDR mode, 1 bit is encoded in each DATA_CODE_ADR
derived code symbol transmitted. (As in the CYWUSB6934
standard modes.)
Both 64-chip and 32-chip DATA_CODE_ADR codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
sent in the same mode. In general, lower data rates reduces
packet error rate in any given environment.
By combining the DATA_CODE_ADR code lengths and data
transmission modes described above, the CYRF69213 IC
supports the following data rates:
1000-kbps (GFSK)
250-kbps (32-chip 8DR)
125-kbps (64-chip 8DR)
62.5-kbps (32-chip DDR)
31.25-kbps (64-chip DDR)
15.625-kbps (64-chip SDR)
Lower data rates typically provide longer range and/or a more
robust link.
Link Layer Modes
The CYRF69213 IC device supports the following data packet
framing features:
SOP
– Packets begin with a 2-symbol Start of Packet (SOP)
marker. This is required in GFSK and 8DR modes, but is
optional in DDR mode and is not supported in SDR mode; if
framing is disabled then an SOP event is inferred whenever
two
successive
correlations
SOP_CODE_ADR code used for the SOP is different from that
used for the ‘body’ of the packet, and if desired may be a
different length. SOP must be configured to be the same
length on both sides of the link.
EOP
– There are two options for detecting the end of a packet.
If SOP is enabled, then a packet length field may be enabled.
GFSK and 8DR must enable the length field. This is the first
8 bits after the SOP symbol, and is transmitted at the payload
data rate. If the length field is enabled, an End of Packet (EOP)
condition is inferred after reception of the number of bytes
defined in the length field, plus two bytes for the CRC16 (if
enabled—see below). The alternative to using the length field
is to infer an EOP condition from a configurable number of
successive non-correlations; this option is not available in
GFSK mode and is only recommended when using SDR
mode.
CRC16
– The device may be configured to append a 16-bit
CRC16 to each packet. The CRC16 uses the USB CRC
polynomial with the added programmability of the seed. If
enabled, the receiver will verify the calculated CRC16 for the
payload data against the received value in the CRC16 field.
The starting value for the CRC16 calculation is configurable,
and the CRC16 transmitted may be calculated using either the
loaded seed value or a zero seed; the received data CRC16
will be checked against both the configured and zero CRC16
seeds.
CRC16 detects the following errors:
Any one bit in error
Any two bits in error (no matter how far apart, which column,
and so on)
Any odd number of bits in error (no matter where they are)
An error burst as wide as the checksum itself
Figure 2
shows an example packet with SOP, CRC16 and
lengths fields enabled.
are
detected.
The
Table 1. Internal PA Output Power Step Table
PA Setting
7
6
5
4
3
2
1
0
Typical Output Power (dBm)
+4
0
–5
–10
–15
–20
–25
–30
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69213-40LTXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CYRF69213A-40LFXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CYRF69213A-40LTXC | 功能描述:射頻收發(fā)器 CYRF69213A-40LTXC RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| CYRF69303 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio-on-Chip LPstar |
| CYRF69303-40LFXC | 功能描述:射頻微控制器 - MCU M8C 8bit 2.4GHz 8KB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:Si100x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LGA-42 安裝風(fēng)格:SMD/SMT 封裝:Tube |
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