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參數(shù)資料
| 型號： | CYRF69213-40LFXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, M0-220, QFN-40 |
| 文件頁數(shù)： | 59/85頁 |
| 文件大?。?/td> | 731K |
| 代理商： | CYRF69213-40LFXC |
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CYRF69213
Document #: 001-07552 Rev. *B
Page 59 of 85
Mnemonic
CHANNEL_ADR
Address
0x00
Bit
7
6
5
4
3
2
1
0
Default
-
1
0
0
1
0
0
0
Read/Write
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Not Used
Channel
Bits 6:0
This field selects the channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 are not valid. The default channel
is a fast channel above the frequency typically used in non-overlapping WiFi systems. Any write to this register will impact the
time it takes the synthesizer to settle.
fast (100-
μ
s) - 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 96
medium (180-
μ
s) - 2 4 8 10 14 16 20 22 26 28 32 34 38 40 44 46 50 52 56 58 62 64 68 70 74 76 78 80 82 84 86 88 90 92 94
slow (270-
μ
s) - 1 5 7 11 13 17 19 23 25 29 31 35 35 37 41 43 47 49 53 55 59 61 65 67 71 73 75 77 79 81 83 85 87 89 91 93 95 97
Usable channels subject to regulation.
D
o not access or modify this register during Transmit or Receive.
Mnemonic
TX_LENGTH_ADR
Address
0x01
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TX Length
Bits 7:0
This register sets the length of the packet to be transmitted. A length of zero is valid, and will transmit a packet with SOP, length
and CRC16 fields (if enabled), but no data field. Packet lengths of more than 16 bytes will require that some data bytes be writ-
ten after transmission of the packet has begun. Typically, length is updated prior to setting TX GO. The maximum packet length
for all packets is 40 bytes except for framed 64-chip DDR where the maximum packet length is 16 bytes.
Maximum packet length is limited by the delta between the transmitter and receiver crystals of 60-ppm or better.
Mnemonic
TX_CTRL_ADR
Address
0x02
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TX GO
TX CLR
TXB15
IRQEN
TXB8
IRQEN
TXB0
IRQEN
TXBERR
IRQEN
TXC
IRQEN
TXE
IRQEN
Bit 7
Start Transmission. Setting this bit triggers the transmission of a packet. Writing a 0 to this flag has no effect. This bit is cleared
automatically at the end of packet transmission. The transmit buffer may be loaded either before or after setting this bit. If data
is loaded after setting this bit, the length of time available to load the buffer depends on the starting state (sleep, idle or synth),
the length of the SOP code, the length of preamble, and the packet data rate. For example, if starting from idle mode on a fast
channel in 8DR mode with 32-chip SOP codes the time available is 100
μ
s (synth start) + 32
μ
s (preamble) + 64
μ
s (SOP
length) + 32
μ
s (length byte) = 228
μ
s. If there are no bytes in the TX buffer at the end of transmission of the length field, a
TXBERR IRQ will occur.
Clear TX Buffer. Writing a 1 to this register clears the transmit buffer. Writing a 0 to this bit has no effect. The previous packet
may be retransmitted by setting TX GO and not setting this bit. A new transmit packet may be loaded and transmitted without
setting this bit if TX GO is set after the new packet is loaded to the buffer. If the TX_BUFFER_ADR is to be loaded after the TX
GO bit has been set, then this bit should be set before loading a new transmit packet to the buffer and before TX GO is set.
Buffer Not Full Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Buffer Half Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Buffer Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Buffer Error Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Transmission Complete Interrupt Enable. See TX_IRQ_STATUS_ADR for description. TXC IRQEN and TXE IRQEN must be
set together.
Transmit Error Interrupt Enable. See TX_IRQ_STATUS_ADR for description. TXC IRQEN and TXE IRQEN must be set
together.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69213-40LTXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CYRF69213A-40LFXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CYRF69213A-40LTXC | 功能描述:射頻收發(fā)器 CYRF69213A-40LTXC RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| CYRF69303 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio-on-Chip LPstar |
| CYRF69303-40LFXC | 功能描述:射頻微控制器 - MCU M8C 8bit 2.4GHz 8KB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:Si100x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:24 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LGA-42 安裝風(fēng)格:SMD/SMT 封裝:Tube |
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