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參數(shù)資料
| 型號(hào)： | CYRF69213-40LFXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, LEAD FREE, M0-220, QFN-40 |
| 文件頁數(shù)： | 62/85頁 |
| 文件大?。?/td> | 731K |
| 代理商： | CYRF69213-40LFXC |
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CYRF69213
Document #: 001-07552 Rev. *B
Page 62 of 85
Mnemonic
RX_IRQ_STATUS_ADR
Address
1
0x07
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R
R
R
R
R
R
R
Function
RXOW IRQ
RSVD
RXB16 IRQ
RXB8 IRQ
RXB1 IRQ
RXBERR RQ
RXC IRQ
RXE IRQ
The state of all IRQ Status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state
whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags
may change value at different times in response to a single event). In particular, standard error handling is only effective if the premature
termination of a transmission due to an exception does not leave the device in an inconsistent state.
Bit 7
Receive Overwrite Interrupt Status. This IRQ is triggered when the receive buffer is overwritten by a packet being received
before the previous packet has been read from the buffer. This bit is cleared by writing any value to this register. This condition
is only possible when the RXOW EN bit in RX_CFG_ADR is set. This bit must be written ‘1’ by firmware before the new packet
may be read from the receive buffer.
Bit 6
Reserved. Must not be set.
Bit 5
Receive Buffer Full Interrupt Status. This bit is set whenever the receive buffer is full, and cleared otherwise.
Bit 4
Receive Buffer Half Full Interrupt Status. This bit is set whenever there are eight or more bytes remaining in the receive buffer.
Firmware must read exactly eight bytes when reading RXB8 IRQ. It is possible, in rare cases, that the last byte of a packet may
remain in the buffer even though the RXB1_IRQ flag has cleared. This can ONLY happen on the last byte of a packet and only
if the packet data is being read out of the buffer while the packet is still being received. The flag is trustworthy under all other
conditions, and for all bytes prior to the last. When using RXB1_IRQ and unloading the packet data during reception, the user
should be sure to check the RX_COUNT_ADR value after the RXC/RXE is set and unload the last remaining byte if the number
of bytes unloaded is less than the reported count, even though the RXB1_IRQ is not set
Bit 3
Receive Buffer Not Empty Interrupt Status. This bit is set at any time that there are 1 or more bytes in the receive buffer, and
cleared when the receive buffer is empty. RXB1 IRQ must not be set when RXB8 IRQ is set and vice versa.
Bit 2
Receive Buffer Error Interrupt Status. This IRQ is triggered in one of two ways: (1) When the receive buffer is empty and there
is an attempt to read data; (2) When the receive buffer is full and more data is received. This flag is cleared when RX GO is set
and a SOP is received.
Bit 1
Packet Receive Complete Interrupt Status. This IRQ is triggered when a packet has been received. If transaction mode is
enabled, then this bit is not set until after transmission of the ACK. If transaction mode is not enabled then this bit is set as soon
as a valid packet is received. This bit is cleared when this register is read. RXC IRQ and RXE IRQ flags may change value at
different times in response to a single event. There are cases when this bit is not triggered when ACK EN = 1 and there is an
error in reception. Therefore, firmware should examine RXC IRQ, RXE IRQ, and CRC 0 to determine receive status. If the first
read of this register returns RXC IRQ = 1 and RXE IRQ = 0 then firmware must execute a second read to this register to deter-
mine if an error occurred by examining the status of RXE IRQ. If the first read of this register returns RXC IRQ = 1 and RXE IRQ
= 1 then the firmware must not execute a second read to this register for a given transaction.
Bit 0
Receive Error Interrupt Status. This IRQ is triggered when there is an error in reception. It is triggered whenever a packet is
received with a bad CRC16, an unexpected EOP is detected, a packet type (data or ACK) mismatch, or a packet is dropped
because the receive buffer is still not empty when the next packet starts. The exact cause of the error may be determined by
reading RX_STATUS_ADR. This bit is cleared when this register is read.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69213-40LTXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CYRF69213A-40LFXC | 功能描述:8位微控制器 -MCU Programmable Radio on Chip Low Power RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| CYRF69213A-40LTXC | 功能描述:射頻收發(fā)器 CYRF69213A-40LTXC RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| CYRF69303 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio-on-Chip LPstar |
| CYRF69303-40LFXC | 功能描述:射頻微控制器 - MCU M8C 8bit 2.4GHz 8KB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:Si100x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LGA-42 安裝風(fēng)格:SMD/SMT 封裝:Tube |
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