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參數(shù)資料
| 型號： | CY7C1381D-133BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 512K X 36 CACHE SRAM, 6.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 477K |
| 代理商： | CY7C1381D-133BZXC |
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PRELIMINARY
CY7C1381D
CY7C1383D
Document #: 38-05544 Rev. *A
Page 6 of 29
Pin Definitions
Name
I/O
Input-
Description
A
0
, A
1
, A
Synchronous
Address Inputs used to select one of the address location
s. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3[2]
are sampled active.
A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW
. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW
. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
Clock Input
. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
2
and CE
3[2]
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.CE
1
is
sampled only when a new external address is loaded.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3[2]
to select/deselect the device. CE
2
is sampled only when a new external
address is loaded.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
and
CE
to select/deselect the device.
CE
3
is sampled only when a new external
address is loaded.
Output Enable, asynchronous input, active LOW
. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK
. When asserted, it automat-
ically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW
.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW
.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Byte Write Enable Input, active LOW
. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
ZZ “sleep” Input, active HIGH
. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQ
and DQP
are placed in a tri-state condition.The
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to DQ
s
.
During write sequences, DQP
X
is controlled by BW
X
correspondingly.
Selects Burst Order
. When tied to GND selects linear burst sequence. When tied to V
DD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
Power supply inputs to the core of the device
.
I/O Power Supply
Power supply for the I/O circuitry
.
Ground
Ground for the core of the device
.
BW
A
, BW
B
BW
C
, BW
D
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Input-
Synchronous
GW
CLK
CE
1
CE
2
Input-
Synchronous
CE
3[2]
Input-
Synchronous
OE
Input-
Asynchronous
ADV
Input-
Synchronous
Input-
Synchronous
ADSP
ADSC
Input-
Synchronous
BWE
Input-
Synchronous
Input-
Asynchronous
ZZ
DQ
s
I/O-
Synchronous
DQP
X
I/O-
Synchronous
Input-Static
MODE
V
DD
V
DDQ
V
SS
Power Supply
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