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參數(shù)資料
| 型號： | CY7C1381D-133BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 512K X 36 CACHE SRAM, 6.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 21/29頁 |
| 文件大?。?/td> | 477K |
| 代理商： | CY7C1381D-133BZXC |
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PRELIMINARY
CY7C1381D
CY7C1383D
Document #: 38-05544 Rev. *A
Page 21 of 29
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
WEH
t
ADVH
t
DH
t
CEH
Notes:
18.Tested initially and after any design or process change that may affect these parameters.
19.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
( minimum) initially, before a read or write operation
can be initiated.
20.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
[A:D]
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ADSP, ADSC Hold After CLK Rise
GW,BWE, BW
[A:D]
Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
Switching Characteristics
Over the Operating Range (continued)
[20, 21]
Parameter
Description
133 MHz
Min.
100 MHz
Min.
Unit
Max.
Max.
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| CY7C1383D | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1381DV25-133AXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1381F-133BGC | 功能描述:靜態(tài)隨機存取存儲器 512Kx36 3.3V Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1381F-133BGCT | 功能描述:靜態(tài)隨機存取存儲器 512Kx36 3.3V Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1381S-133AXC | 功能描述:靜態(tài)隨機存取存儲器 CY7C1381S-133AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1381XC | 制造商:Cypress Semiconductor 功能描述: |
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