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參數(shù)資料
| 型號： | CC113LRTKT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, VQFN-20 |
| 文件頁數(shù)： | 54/75頁 |
| 文件大小： | 1454K |
| 代理商： | CC113LRTKT |
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CC113L
SWRS108A
Page 58 of 68
0x1A: BSCFG - Bit Synchronization Configuration
Bit
Field Name
Reset
R/W
Description
7:6
BS_PRE_KI[1:0]
1 (01)
R/W
The clock recovery feedback loop integral gain to be used before a sync word is
detected (used to correct offsets in data rate):
Setting
Clock recovery loop integral gain before sync word
0 (00)
KI
1 (01)
2KI
2 (10)
3KI
3 (11)
4KI
5:4
BS_PRE_KP[1:0]
2 (10)
R/W
The clock recovery feedback loop proportional gain to be used before a sync word
is detected.
Setting
Clock recovery loop proportional gain before sync word
0 (00)
KP
1 (01)
2KP
2 (10)
3KP
3 (11)
4KP
3
BS_POST_KI
1
R/W
The clock recovery feedback loop integral gain to be used after a sync word is
detected.
Setting
Clock recovery loop integral gain after sync word
0
Same as BS_PRE_KI
1
KI /2
2
BS_POST_KP
1
R/W
The clock recovery feedback loop proportional gain to be used after a sync word is
detected.
Setting
Clock recovery loop proportional gain after sync word
0
Same as BS_PRE_KP
1
KP
1:0
BS_LIMIT[1:0]
0 (00)
R/W
The saturation point for the data rate offset compensation algorithm:
Setting
Data rate offset saturation (max data rate difference)
0 (00)
±0 (No data rate offset compensation performed)
1 (01)
±3.125 % data rate offset
2 (10)
±6.25 % data rate offset
3 (11)
±12.5 % data rate offset
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