參數(shù)資料
型號(hào)： CC113LRTKT
廠商： TEXAS INSTRUMENTS INC
元件分類： 無繩電話/電話
英文描述： TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20
封裝： 4 X 4 MM, GREEN, PLASTIC, VQFN-20
文件頁數(shù)： 11/75頁
文件大?。?/td> 1454K
代理商： CC113LRTKT
CC113L
SWRS108A
Page 19 of 68
7.6
PCB Layout Recommendations
The top layer should be used for signal
routing, and the open areas should be filled
with metallization connected to ground using
several vias.
The area under the chip is used for grounding
and shall be connected to the bottom ground
plane with several vias for good thermal
performance and sufficiently low inductance to
ground.
In the CC113LEM reference designs ([10] and
[11]), 5 vias are placed inside the exposed die
attached pad. These vias should be “tented”
(covered with solder mask) on the component
side of the PCB to avoid migration of solder
through the vias during the solder reflow
process.
The solder paste coverage should not be
100%. If it is, out gassing may occur during the
reflow process, which may cause defects
(splattering, solder balling). Using “tented” vias
reduces the solder paste coverage below
100%. See Figure 11 for top solder resist and
top paste masks.
Each decoupling capacitor should be placed
as close as possible to the supply pin it is
supposed
to
decouple.
Each
decoupling
capacitor should be connected to the power
line (or power plane) by separate vias. The
best routing is from the power line (or power
plane) to the decoupling capacitor and then to
the CC113L supply pin. Supply power filtering is
very important.
Each decoupling capacitor ground pad should
be connected to the ground plane by separate
vias. Direct connections between neighboring
power pins will increase noise coupling and
should
be
avoided
unless
absolutely
necessary.
Routing
in
the
ground
plane
underneath the chip or the balun/RF matching
circuit, or between the chips ground vias and
the decoupling capacitors ground vias should
be avoided. This improves the grounding and
ensures the shortest possible current return
path.
Avoid routing digital signals with sharp edges
close to XOSC_Q1 PCB track or underneath
the crystal Q1 pad as this may shift the crystal
dc operating point and result in duty cycle
variation.
The external components should ideally be as
small as possible (0402 is recommended) and
surface
mount
devices
are
highly
recommended. Please note that components
with different sizes than those specified may
have differing characteristics.
Precaution should be used when placing the
microcontroller
in
order
to
avoid
noise
interfering with the RF circuitry.
A CC11xL Development Kit with a fully
assembled
CC113L Evaluation Module is
available. It is strongly advised that this
reference layout is followed very closely in
order to get the best performance. The
schematic, BOM and layout Gerber files are all
available from the TI website ([10] and [11]).
Figure 11: Left: Top Solder Resist Mask (Negative). Right: Top Paste Mask. Circles are Vias
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