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參數(shù)資料
| 型號： | CC113LRTKT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, VQFN-20 |
| 文件頁數(shù)： | 14/75頁 |
| 文件大小： | 1454K |
| 代理商： | CC113LRTKT |
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CC113L
SWRS108A
Page 21 of 68
9
Configuration Software
CC113L can be configured using the SmartRF
Studio software [4]. The SmartRF Studio
software is highly recommended for obtaining
optimum register settings, and for evaluating
performance and functionality.
After chip reset, all the registers have default
values as shown in the tables in Section 26.
The optimum register setting might differ from
the default value. After a reset all registers that
shall be different from the default value
therefore needs to be programmed through
the SPI interface.
10 4-wire Serial Configuration and Data Interface
CC113L is configured via a simple 4-wire SPI-
compatible interface (SI, SO, SCLK and CSn)
where CC113L is the slave. This interface is also
used to read buffered data. All transfers on the
SPI interface are done most significant bit first.
All transactions on the SPI interface start with
a header byte containing a R/W
bit, a burst
access bit (B), and a 6-bit address (A5 - A0).
The CSn pin must be kept low during transfers
on the SPI bus. If CSn goes high during the
transfer of a header byte or during read/write
from/to
a
register,
the
transfer
will
be
cancelled. The timing for the address and data
transfer on the SPI interface is shown in Figure
When CSn is pulled low, the MCU must wait
until CC113L SO pin goes low before starting to
transfer the header byte. This indicates that
the crystal is running. Unless the chip was in
the SLEEP or XOFF states, the SO pin will
always go low immediately after taking CSn
low.
0
A5
A4
A3
A2
A0
A1
DW7
1
Read from register:
Write to register:
Hi-Z
X
SCLK:
CSn:
SI
SO
SI
SO
Hi-Z
t
sp
t
ch
t
cl
t
sd
t
hd
t
ns
X
Hi-Z
X
Hi-Z
S7
X
DW6
DW5
DW4
DW3
DW2
DW1
DW0
B
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
B
A5
A4
A3
A2
A1
A0
S7
B
S5
S4
S3
S2
S1
S0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Figure 13: Configuration Registers Write and Read Operations
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