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參數(shù)資料
| 型號： | CC113LRTKT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, VQFN-20 |
| 文件頁數(shù)： | 17/75頁 |
| 文件大小： | 1454K |
| 代理商： | CC113LRTKT |
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CC113L
SWRS108A
Page 24 of 68
The command strobe registers are accessed
by transferring a single header byte (no data is
being transferred). That is, only the R/W
bit,
the burst access bit (set to 0), and the six
address bits (in the range 0x30 through 0x3D)
are written. The R/W
bit should be set to one if
the FIFO_BYTES_AVAILABLE field in the
status byte should be interpreted.
When writing command strobes, the status
byte is sent on the SO pin.
A command strobe may be followed by any
other SPI access without pulling CSn high.
However, if an SRES strobe is being issued,
one will have to wait for SO to go low again
before the next header byte can be issued as
shown in Figure 14. The command strobes are
executed immediately, with the exception of
executed when CSn goes high.
SI
HeaderSRES
HeaderAddr
Data
SO
CSn
Figure 14: SRES Command Strobe
10.5 RX FIFO Access
The 64-byte RX FIFO is accessed through the
0x3F address. The RX FIFO is write-only and
the R/W
bit should therefore be one.
The burst bit is used to determine if the
RX FIFO access is a single byte access or a
burst access. The single byte access method
expects a header byte with the burst bit set to
zero and one data byte. After the data byte, a
new header byte is expected; hence, CSn can
remain low. The burst access method expects
one header byte and then consecutive data
bytes until terminating the access by setting
CSn high.
The
following
header
bytes
access
the
RX FIFO:
0xBF: Single byte access to RX FIFO
0xFF: Burst access to RX FIFO
The RX FIFO may be flushed by issuing a
SFRX command strobe. A SFRX command
strobe can only be issued in the IDLE, or
RXFIFO_OVERFLOW states. The RX FIFO is
flushed when going to the SLEEP state.
Figure 15 gives a brief overview of different
register access types possible.
HeaderStrobe
HeaderReg
Data
HeaderReg
HeaderReg n
Datan
Data n + 1
DataByte 1
DataByte 0
HeaderRX FIFO
HeaderReg
Data
HeaderStrobe
Data
HeaderReg
Data
Datan + 2
DataByte 2
DataByte n - 1
DataByte n
HeaderReg
Data
HeaderStrobe
HeaderRX FIFO
DataByte 0
DataByte 1
Command strobe(s)
Read or write register(s)
Read or write
consecutive register(s)
Write n + 1 bytes to the
RX FIFO
Combinations
Csn
. . . . . . . . .
. . . .
. . . . . . . . .
Figure 15: Register Access Types
Note: An SIDLE strobe will clear all
pending command strobes until IDLE
state is reached. This means that if for
example an SIDLE strobe is issued
while the radio is in RX state, any other
command strobes issued before the
radio
reaches
IDLE
state
will
be
ignored.
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