參數(shù)資料
型號： CC113LRTKT
廠商： TEXAS INSTRUMENTS INC
元件分類： 無繩電話/電話
英文描述： TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQCC20
封裝： 4 X 4 MM, GREEN, PLASTIC, VQFN-20
文件頁數(shù)： 15/75頁
文件大?。?/td> 1454K
代理商： CC113LRTKT
CC113L
SWRS108A
Page 22 of 68
Parameter
Description
Min
Max
Units
fSCLK
SCLK frequency
100 ns delay inserted between address byte and data byte (single access), or between
address and data, and between each data byte (burst access).
-
10
MHz
SCLK frequency, single access. No delay between address and data byte
-
9
SCLK frequency, burst access. No delay between address and data byte, or between data
bytes
-
6.5
tsp,pd
CSn low to positive edge on SCLK, in power-down mode
150
-
s
tsp
CSn low to positive edge on SCLK, in active mode
20
-
ns
tch
Clock high
50
-
ns
tcl
Clock low
50
-
ns
trise
Clock rise time
-
40
ns
tfall
Clock fall time
-
40
ns
tsd
Setup data (negative SCLK edge) to positive edge on SCLK
(tsd applies between address and data bytes, and between data bytes)
Single access
55
-
ns
Burst access
76
-
thd
Hold data after positive edge on SCLK
20
-
ns
tns
Negative edge on SCLK to CSn high.
20
-
ns
Table 15: SPI Interface Timing Requirements
10.1 Chip Status Byte
When the header byte, data byte, or command
strobe is sent on the SPI interface, the chip
status byte is sent by the CC113L on the SO pin.
The status byte contains key status signals,
useful for the MCU. The first bit, s7, is the
CHIP_RDYn signal and this signal must go low
before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is
running.
Bits 6, 5, and 4 comprise the STATE value.
This value reflects the state of the chip. The
XOSC and power to the digital core are on in
the IDLE state, but all other modules are in
power down. The frequency and channel
configuration should only be updated when the
chip is in this state.
The last four bits (3:0) in the status byte
contains
FIFO_BYTES_AVAILABLE.
For
these bits to give any valid information, the
R/W
bit in the header byte must be set to 1.
The FIFO_BYTES_AVAILABLE field will then
contain the number of bytes that can be read
from
the
RX
FIFO.
When
FIFO_BYTES_AVAILABLE=15, 15 or more
bytes can be read. The RX FIFO should not be
emptied before the complete packet has been
received (see the CC113L Errata Notes [3] for
more details).
Table 16 gives a status byte summary.
Note: The minimum tsp,pd figure in Table 15 can be used in cases where the user does not read
the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-
down depends on the start-
up time of the crystal being used. The 150 μs in Table 15 is the
crystal oscillator start-up time measured on [1] and [2] using crystal AT-41CD2 from NDK.
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