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| 型號(hào)： | B80546PG0721M |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478 |
| 文件頁(yè)數(shù)： | 74/80頁(yè) |
| 文件大小： | 1845K |
| 代理商： | B80546PG0721M |
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77
XMEGA C3 [DATASHEET]
8361D–AVR–07/2013
35.13.5 Internal Phase Locked Loop (PLL) characteristics
Table 35-23. Internal PLL characteristics.
Note:
1.
The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
35.13.6 External clock characteristics
Figure 35-3. External clock drive waveform .
Table 35-24. External clock(1).
Notes:
1.
System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2.
The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
fIN
Input frequency
Output frequency must be within fOUT
0.4
64
MHz
fOUT
Output frequency (1)
VCC= 1.6 - 1.8V
20
48
VCC= 2.7 - 3.6V
20
128
Start-up time
25
μs
Re-lock time
25
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
1/tCK
Clock frequency(2)
VCC = 1.6 - 1.8V
0
90
MHz
VCC = 2.7 - 3.6V
0
142
tCK
Clock period
VCC = 1.6 - 1.8V
11
ns
VCC = 2.7 - 3.6V
7.0
tCH/CL
Clock high/low time
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
VIL/IH
Low/high level input voltage
V
t
CK
Reduction in period time from one
clock cycle to the next
10
%
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