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參數(shù)資料
| 型號： | B80546PG0721M |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478 |
| 文件頁數(shù)： | 20/80頁 |
| 文件大?。?/td> | 1845K |
| 代理商： | B80546PG0721M |
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Datasheet
27
Electrical Specifications
Table 12. GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage
0.0
GTLREF – (0.10 * V
CC)V
2, 3
2.
V
IL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3.
The V
CC referred to in these specifications is the instantaneous VCC.
V
IH
Input High Voltage
GTLREF + (0.10 * V
CC)VCC
V
3, 4
4.
V
IH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
V
OH
Output High Voltage
0.90*V
CC
V
CC
V
I
OL
Output Low Current
N/A
V
CC/[(0.50*RTT
_MIN)+(RON_MIN)]
A
I
LI
Input Leakage Current
N/A
± 200
A
5
5.
Leakage to V
SS with pin held at VCC.
I
LO
Output Leakage Current
N/A
± 200
A
6
6.
Leakage to V
CC with pin held at 300 mV.
RON
Buffer On Resistance
8
12
Table 13. Asynchronous GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage
0.0
V
CC/2 – (0.10 * VCC)V
2, 3
2.
VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3.
LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals,
V
IH = GTLREF + (0.10 * VCC) and VIL= GTLREF - (0.10 * Vcc).
V
IH
Input High Voltage
V
CC/2 + (0.10 * VCC)VCC
V
3, 4, 5
4.
VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5.
The V
CC referred to in these specifications refers to instantaneous VCC.
V
OH
Output High Voltage
0.90*V
CC
V
CC
V
5, 6
6.
All outputs are open drain.
I
OL
Output Low Current
V
CC/[(0.50*RTT
_MIN)+(RON_MIN)]
A
7
7.
The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
I
LI
Input Leakage Current
N/A
± 200
A
8
8.
Leakage to Vss with pin held at V
CC.
I
LO
Output Leakage Current
N/A
± 200
A
RON
Buffer On Resistance
8
12
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