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參數(shù)資料
| 型號： | B80546PG0721M |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478 |
| 文件頁數(shù)： | 11/80頁 |
| 文件大小： | 1845K |
| 代理商： | B80546PG0721M |
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Datasheet
19
Electrical Specifications
2.6
Asynchronous GTL+ Signals
Legacy input signals (such as A20M#, IGNNE#, INIT#, SMI#, SLP#, and STPCLK#) use CMOS
input buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the
outputs are not actively driven high (during a logical 0-to-1 transition) by the processor. These
signals do not have setup or hold time specifications in relation to BCLK[1:0].
2.7
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the processor be first in the TAP chain and followed by any other components
within the system. A translation buffer should be used to connect to the rest of the chain unless one
of the other components is capable of accepting an input of the appropriate voltage level. Similar
considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each signal
may be required, with each driving a different voltage level.
Table 5.
Signal Characteristics
Signals with R
TT
Signals with No R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BOOTSELECT1, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,
OPTIMIZED/COMPAT#1, PROCHOT#, REQ[4:0]#,
RS[2:0]#, RSP#, TRDY#
NOTES:
1.
The OPTIMIZED/COMPAT# and BOOTSELECT pins have a 500–5000
pull-up to V
CCVID rather than RTT.
A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[1:0],
COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,
LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,
SKTOCC#, SLP#, SMI#, STPCLK#, TDO,
TESTHI[12:0], THERMDA, THERMDC,
THERMTRIP#, VID[5:0], VIDPWRGD,
GTLREF[3:0], TCK, TDI, TRST#, TMS
Open Drain Signals2
2.
Signals that do not have R
TT, nor are actively driven to their high-voltage level.
BSEL[1:0], VID[5:0], THERMTRIP#, FERR#/PBE#,
IERR#, BPM[5:0]#, BR0#, TDO
Table 6.
Signal Reference Voltages
GTLREF
VCC/2
VCCVID/2
BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#, BNR#,
HIT#, HITM#, MCERR#, PROCHOT#, BR0#, A[35:0]#, ADS#,
ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#,
DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
LOCK#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
A20M#, IGNNE#, INIT#,
PWRGOOD1, SLP#,
SMI#, STPCLK#, TCK1,
NOTES:
1.
These signals also have hysteresis added to the reference voltage. See Table 14 for more information.
VIDPWRGD,
BOOTSELECT,
OPTIMIZED/
COMPAT#
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