參數(shù)資料
型號： B80546PG0721M
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478
封裝： 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478
文件頁數(shù)： 36/80頁
文件大?。?/td> 1845K
代理商： B80546PG0721M
42
XMEGA C3 [DATASHEET]
8361D–AVR–07/2013
24.
USART
24.1 Features
Three identical USART peripherals
Full-duplex operation
Asynchronous or synchronous operation
– Synchronous clock rates up to 1/2 of the device clock frequency
– Asynchronous clock rates up to 1/8 of the device clock frequency
Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
Fractional baud rate generator
– Can generate desired baud rate from any system clock frequency
– No need for external oscillator with certain frequencies
Built-in error detection and correction schemes
– Odd or even parity generation and parity check
– Data overrun and framing error detection
– Noise filtering includes false start bit detection and digital low-pass filter
Separate interrupts for
– Transmit complete
– Transmit data register empty
– Receive complete
Multiprocessor communication mode
– Addressing scheme to address a specific devices on a multidevice bus
– Enable unaddressed devices to automatically ignore all frames
Master SPI mode
– Double buffered operation
– Operation up to 1/2 of the peripheral clock frequency
IRCOM module for IrDA compliant pulse modulation/demodulation
24.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2kbps.
PORTC, PORTD, and PORTE each has one USART. Notation of these peripherals are USARTC0, USARTD0 and
USARTE0, respectively.
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