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參數(shù)資料
| 型號： | B80546PG0721M |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478 |
| 文件頁數(shù)： | 10/80頁 |
| 文件大?。?/td> | 1845K |
| 代理商： | B80546PG0721M |
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18
Datasheet
Electrical Specifications
2.5
FSB Signal Groups
The FSB signals have been combined into groups by buffer type. GTL+ input signals have
differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+
Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly,
"GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals that are dependent on the rising edge of
BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals that
are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0.
Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time
during the clock cycle. Table 4 identifies which signals are common clock, source synchronous,
and asynchronous.
Table 4.
FSB Pin Groups
Signal Group
Type
Signals1
NOTES:
1.
Refer to Section 4.2 for signal descriptions.
GTL+ Common Clock
Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
GTL+ Common Clock I/O
Synchronous to
BCLK[1:0]
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,
DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#
GTL+ Source
Synchronous I/O
Synchronous to
associated strobe
SignalsAssociated Strobe
REQ[4:0]#, A[16:3]#2ADSTB0#
A[35:17]#2ADSTB1#
D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
D[47:32]#, DBI2# DSTBP2#, DSTBN2#
D[63:48]#, DBI3# DSTBP3#, DSTBN3#
2.
The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration
options. See Section 6.1 for details.
GTL+ Strobes
Synchronous to
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
Asynchronous GTL+
Input
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
SLP#, STPCLK#
Asynchronous GTL+
Output
FERR#/PBE#, IERR#, THERMTRIP#
Asynchronous GTL+
Input/Output
PROCHOT#
TAP Input
Synchronous to TCK
TCK, TDI, TMS, TRST#
TAP Output
Synchronous to TCK
TDO
FSB Clock
Clock
BCLK[1:0], ITP_CLK[1:0]3
3.
In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
Power/Other
VCC, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA,
GTLREF[3:0], COMP[1:0], RESERVED, TESTHI[12:0],
THERMDA, THERMDC, VCC_SENSE, VSS_SENSE,
VCCVID, VCCVIDLB, BSEL[1:0], SKTOCC#, DBR#3,
VIDPWRGD, BOOTSELECT, OPTIMIZED/COMPAT#,
PWRGOOD
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