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參數(shù)資料
| 型號： | B80546PG0721M |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478 |
| 文件頁數(shù)： | 27/80頁 |
| 文件大小： | 1845K |
| 代理商： | B80546PG0721M |
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34
XMEGA C3 [DATASHEET]
8361D–AVR–07/2013
17.
TC2 – Timer/Counter Type 2
17.1 Features
Eight eight-bit timer/counters
– Four Low-byte timer/counter
– Four High-byte timer/counter
Up to eight compare channels in each Timer/Counter 2
– Four compare channels for the low-byte timer/counter
– Four compare channels for the high-byte timer/counter
Waveform generation
– Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
17.2 Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation
(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of
PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and
compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event
system. The counters are always counting down.
PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2),
TCD2, TCE2 and TCF2, respectively.
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