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參數資料
| 型號： | B80546PG0721M |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478 |
| 文件頁數： | 6/80頁 |
| 文件大?。?/td> | 1845K |
| 代理商： | B80546PG0721M |
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14
Datasheet
Electrical Specifications
2.2.3
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.
As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0]
frequency. No user intervention is necessary, and the processor will automatically run at the speed
indicated on the package. The processor uses a differential clocking implementation.
2.3
Voltage Identification
The VID specification for the processor is supported by the Voltage Regulator-Down (VRD) 10.0
Design Guidelines for Desktop Socket 478. The voltage set by the VID pins is the maximum
voltage allowed by the processor. A minimum voltage is provided in Table 9 and changes with
frequency. This allows processors running at a higher frequency to have a relaxed minimum
voltage specification. The specifications have been set such that one voltage regulator can work
with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two devices at
the same speed may have different VID settings.
The processor uses six voltage identification pins, VID[5:0], to support automatic selection of
power supply voltages. Table 3 specifies the voltage level corresponding to the state of VID[5:0].
A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to low voltage level. If the processor
socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage
that is requested, it must disable itself. See the Voltage Regulator-Down (VRD) 10.0 Design
Guidelines for Desktop Socket 478 for more details.
Power source characteristics must be guaranteed to be stable when the supply to the voltage
regulator is stable.
The processor’s Voltage Identification circuit requires an independent 1.2 V supply and some other
power sequencing considerations.
Table 2.
Core Frequency to FSB Multiplier Configuration
Multiplication of System
Core Frequency to FSB
Frequency
Core Frequency
(133 MHz BCLK/533 MHz FSB)
Core Frequency
(200 MHz BCLK/800 MHz FSB)
Notes
1/14
RESERVED
2.80E GHz
1/15
RESERVED
3E GHz
1/16
RESERVED
3.20E GHz
1
NOTES:
1.
Individual processors operate only at or below the rated frequency.
1/17
RESERVED
3.40E GHz
1/18
RESERVED
1/19
RESERVED
1/20
RESERVED
1/21
2.80A GHz
RESERVED
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