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參數(shù)資料
| 型號： | B80546PG0721M |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR, CPGA478 |
| 封裝： | 1.27 MM PITCH, FLIP CHIP, MICRO PGA-478 |
| 文件頁數(shù)： | 5/80頁 |
| 文件大?。?/td> | 1845K |
| 代理商： | B80546PG0721M |
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Datasheet
13
Electrical Specifications
2
Electrical Specifications
2.1
Power and Ground Pins
For clean on-chip power distribution, the processor has 85 VCC (power) and 179 VSS (ground)
pins. All power pins must be connected to VCC, while all VSS pins must be connected to a system
ground plane.The processor VCC pins must be supplied by the voltage determined by the VID
(Voltage identification) pins.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large current swings between low and full power states. This may cause voltages on
power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 9. Failure to do so can result in timing violations or reduced lifetime
of the component. For further information and design guidelines, refer to the appropriate platform
design guide, and the Voltage Regulator-Down (VRD) 10.0 Design Guidelines for Desktop Socket
478.
2.2.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the
large current swings when the part is powering on, or entering/exiting low power states, must be
provided by the voltage regulator solution (VR). For more details on this topic, refer to the
appropriate platform design guide, and the Voltage Regulator-Down (VRD) 10.0 Design Guidelines
for Desktop Socket 478.
2.2.2
FSB GTL+ Decoupling
The processor integrates signal termination on the die as well as incorporating high frequency
decoupling capacitance on the processor package. Decoupling must also be provided by the system
baseboard for proper GTL+ bus operation. For more information, refer to the appropriate platform
design guide.
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