參數(shù)資料
型號(hào)： AX88196BLF
廠商： ASIX Electronics Corporation
英文描述： Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface
中文描述： 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個(gè)10/100M快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 9/86頁(yè)
文件大?。?/td> 551K
代理商： AX88196BLF
ASIX ELECTRONICS CORPORATION
9
AX88196BLF
2.6 MII pins group
Signal
TXCLK
Type
I/PD
Pin No.
72
Description
Transmit Clock: TXCLK is a continuous clock from PHY. It provides
the timing reference for the transfer of the TXEN and TXD[3:0]
signals from the MII port to the PHY.
Transmit Enable: TXEN is transition synchronously with respect to the
rising edge of TXCLK. TXEN indicates that the port is presenting
nibbles on TXD [3:0] for transmission.
68, 69, 70, 71 Transmit Data: TXD[3:0] is transition synchronously with respect to
the rising edge of TXCLK. For each TXCLK period in which TXEN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
41
Collision: this signal is driven by PHY when collision is detected.
42
Carrier Sense: Asynchronous signal CRS is asserted by the PHY when
either transmit or receive medium is non-idle.
17
Receive Clock: RXCLK is a continuous clock that provides the timing
reference for the transfer of the RXDV and RXD[3:0] signals from the
PHY to the MII port.
19
Receive Data Valid: RXDV is driven by the PHY synchronously with
respect to RXCLK. Asserted high when valid data is present on RXD
[3:0].
29, 30, 31, 32 Receive Data: RXD[3:0] is driven by the PHY synchronously with
respect to RXCLK.
62
Station Management Data Clock: The timing reference for MDIO. All
data transfers on MDIO are synchronized to the rising edge of this
clock.
63
Station Management Data Input/Output: Serial data input/output
transfers from/to the PHYs.
TXEN
O5/8m
73
TXD[3:0]
O5/8m
COL
CRS
I/PD
I/PD
RXCLK
I/PD
RXDV
I/PD
RXD[3:0]
I/PD
MDC
O5/8m
MDIO
B5/PU
Tab - 6 MII pins group
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