參數(shù)資料
型號： AX88196BLF
廠商： ASIX Electronics Corporation
英文描述： Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface
中文描述： 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個10/100M快速以太網(wǎng)控制器
文件頁數(shù)： 30/86頁
文件大?。?/td> 551K
代理商： AX88196BLF
ASIX ELECTRONICS CORPORATION
30
AX88196BLF
4.8.1 Power Management Event Indicators
The external PME signal can be setup as Push-Pull driver or open-drain buffer. And also can be set as active high or
active low. When set the PME_IND bit to a ‘1’, (offset 15h) the external PME signal will be driven active for 60ms
upon detection of a wake-up event. When the PME_IND bit is cleared, the PME signal will be driven continuously
upon detection of a wake-up event. Host can checks which kind of wake-up event activity by reads “Wake up
Control and Status Register”(CR page3 offset 0Ah). Host can writing “Power Management Register”(CR page3
offset 0Bh) or writing a ‘1’ to clear wake-up event activity flags on “Wake up Control and Status Register”(CR
page3 offset 0Ah) to deactivated PME signal.
IRQ_POL (offset 15h)
MPEN (CR page3 offset 0Ah)
ENB
PME
logic
PME_POL (offset 15h)
PME_TYPE (offset 15h)
WUEN (CR page3 offset 0Ah)
Magic Packet Detect event
Wakeup Frame Detect event
ENB
logic
IREQ
IRQ_TYPE (offset 15h)
System interrupt event
PME_IRQ_EN (offset 15h)
IRQ_TYPE (from EEPROM)
IRQ_POL (from EEPROM)
PME_IND (offset 15h)
60ms
Fig - 8 PME and IRQ signal generation
4.9 Device Ready or Busy
There are three kinds of device ready indicator in “Device Status Register” (Offset 17h). Those are indicates
AX88196B internal operation busy. In order to prevent the host access AX88196B in the busy stage, host can to
check the “Device Status Register” before doing some key operations.
When a “0” at the bit-4 (D-RDY) in “Device Status Register” (Offset 17h), indicate the AX88196B in reset state or
power saving state or EEPROM loading state or loop-back mode swapping.
When a “0” at the bit-5 (RD-RDY) in “Device Status Register” (Offset 17h), indicate the remote-DMA-read data
not ready yet, host must not read data port (DP) in this period. The non-ready period only happen when host set a
remote-read command on “Command Register”(CR), and it will be go to ready state when a valid data pop out for
host to reading. Host driver can back-to-back read data port (DP) since checked the RD-RDY was ready. The
maximum of remote-read non-ready period only spend 60ns. Host can ignore to check RD_RDY if host access time
not faster then it.
When a “0” at the bit-6 (RDMA-RDY) in “Device Status Register” (Offset 17h), indicate the remote DMA not
completed yet. This RDMA-RDY will be cleared when host write “Remote Byte Count 0” RBCR0 (CR page0
Offset 0Ah) or “Remote Byte Count 1” RBCR1 (CR page0 Offset 0Bh). The byte counter will down counting when
every data port (DP) access. This RDMA-RDY will be set when byte counter count to zero.
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相關(guān)代理商/技術(shù)參數(shù)
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