參數(shù)資料
型號(hào)： AX88196BLF
廠商： ASIX Electronics Corporation
英文描述： Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface
中文描述： 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個(gè)10/100M快速以太網(wǎng)控制器
文件頁(yè)數(shù)： 38/86頁(yè)
文件大?。?/td> 551K
代理商： AX88196BLF
ASIX ELECTRONICS CORPORATION
38
AX88196BLF
5.1.8 Number Of Collisions Register (NCR)
Page0 Offset 05H (Read)
Field
Name
Description (Default = 00h)
7:4
-
Always zero
3:0
NCR
If no collisions are experienced during a transmission attempt, the COL bit of the TSR will
not be set and the contents of NCR will be zero. If there are excessive collisions, the ABT bit
in the TSR will be set and the contents of NCR will be zero. The NCR is cleared after the
TXP bit in the CR is set.
5.1.9 Transmit Byte Count Register (TBCR1)
Page0 Offset 06H (Write)
Field
Name
Description
7:0
TBCR1
Transmit Byte Count Register.
5.1.10 Current Page Register (CPR)
Page0 Offset 06H (Read)
Field
Name
Description (Default = 4Dh)
7:0
CPR
The Buffer Management Logic as a backup register for reception uses this register
internally. CURR contains the address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive errors. This register is initialized
to the same value as PSTART and should not be written to again unless the controller is
Reset.
5.1.11 Interrupt Status Register (ISR)
Page0 Offset 07H (Read/Write)
Field
Name
Description (Default = 80h)
7
RST
Reset Status:
Set when AX88196B enters reset state (or a wake-up event) and cleared when a start
command is issued to the CR. Writing to this bit is no effect.
6
RDC
Remote DMA Complete
Set when remote DMA operation has been completed. Write this bit to high then reset it.
5
CNT
Counter Overflow
Set when MSB of one or more of the Tally Counters has been set. Write this bit to high
then reset its.
4
OVW
OVERWRITE: Set when receive buffer ring storage resources have been exhausted.
Write this bit to high then reset it.
3
TXE
Transmit Error
Set when packet transmitted with one or more of the following errors
Excessive collisions, Transmit over size and late collision.
Write this bit to high then reset it.
2
RXE
Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
Missed Packet
Write this bit to high then reset it.
1
PTX
Packet Transmitted
Indicates packet transmitted with no error
Write this bit to high then reset it.
0
PRX
Packet Received
Indicates packet received with no error.
Write this bit to high then reset it.
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