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參數(shù)資料
| 型號： | AX88196BLF |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| 中文描述： | 低引腳數(shù)不符合信息產(chǎn)業(yè)部的PCI接口16位產(chǎn)品個10/100M快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 43/86頁 |
| 文件大?。?/td> | 551K |
| 代理商： | AX88196BLF |
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ASIX ELECTRONICS CORPORATION
43
AX88196BLF
5.1.26 Physical Address Register 0 (PAR0)
Page1 Offset 01H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR0
Physical Address Register 0
5.1.27 Physical Address Register 1 (PAR1)
Page1 Offset 02H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR1
Physical Address Register 1
5.1.28 Physical Address Register 2 (PAR2)
Page1 Offset 03H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR2
Physical Address Register 2
5.1.29 Physical Address Register 3 (PAR3)
Page1 Offset 04H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR3
Physical Address Register 3
5.1.30 Physical Address Register 4 (PAR4)
Page1 Offset 05H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR4
Physical Address Register 4
5.1.31 Physical Address Register 5 (PAR5)
Page1 Offset 06H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR5
Physical Address Register 5
The physical address registers are used to compare the destination address of incoming packets for rejecting or
accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the
sequence in PAR0 ~ PAR5 to the bit sequence of the received packet.
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| AX88196L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88613 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
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| AX88615P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-Port 10/100BASE Ethernet Switch |
| AX8863T | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Low-Dropout, 120mA Linear Regulators |
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