參數(shù)資料
型號(hào)： AX88180
廠商： ASIX Electronics Corporation
英文描述： High-Performance Non-PCI 32-bit 10/100/1000M Gigabit Ethernet Controller
中文描述： 高性能非PCI 32位10/100/1000千兆以太網(wǎng)控制器
文件頁(yè)數(shù)： 8/47頁(yè)
文件大小： 420K
代理商： AX88180
AX88180
8
ASIX ELECTRONICS CORPORATION
2.0 Signal Description
2.1 Signal Type Definition
I3:
I2:
I25
O3:
O2:
IO3:
IO2:
TSO:
OD:
PD:
PU:
GND:
VCC3:
VCC2:
I:
O:
IO:
Input, 3.3V with 5V tolerance
Input, 2.5V with 3.3V tolerance
Input 2.5V only
Output, 3.3V
Output, 2.5V
Input/Output, input 3.3V with 5V tolerance
Input/Output, input 2.5V with 3.3V tolerance
Tri-State Output
Open Drain allows multiple devices to share as a wire-OR
Internal 75K Pull Down
Internal 75K Pull Up
Digital Ground
3.3V power
2.5V power
Input only
Output only
Input/Output
2.2 RGMII/MII Interface
Table 1 : RGMII/MII Interface signals group
Pin NO
Pin Description
Pin Name Type
CLK125
I3
51
Free running clock 125MHz from OSC or Giga-PHY.
TXEN
O2, 12mA 66
Transmit Enable:
TXEN is transition synchronously with respect to the rising and falling edge of
TXCX. TXEN indicates that the port is presenting nibbles on TXD [3:0] for
transmission.
TXD[3:0] O2, 12mA 61,62,63,65 Transmit Data:
TXD[3:0] is transition synchronously with respect to the rising and falling edge of
TXCX. In rising edge TXD[3:0] is as general TD[3:0] and falling edge TXD[3:0]
is as TD[7:4]. TD[7:0] is used in AX88180 as byte unit.
TXCX
O2, 12mA 68
125MHz Clock Output:
It is a continuous 125 MHz clock Output to Giga-PHY operating in RGMII mode. It
is a timing reference for TXEN and TXD[3:0]. For normal operation, this pin will
be connected to Giga-PHY.
GTXCLK O2, 12mA 67
125MHz Clock Output:
It is a continuous 125 MHz clock output. This pin is for internal debug purpose only
and should be floating for normal operation.
RXCLK
I2
71
Receive Clock:
RXCLK is a continuous clock that provides the timing reference for RXDV,
RXD[3:0]. This clock is provided from PHY.
RXD[3:0] I2
77,76,75,74 Receive Data:
RXD[3:0] is driven by the PHY synchronously with respect to RXCLK. In rising
edge RXD[3:0] is as RD[3:0] and falling edge is as RD[7:4]. RD[7:0] is used in
AX88180 as byte unit.
RXDV
I2
70
Receive Data Valid:
RXDV is driven by the PHY synchronously with respect to RXCLK in rising and
falling edge. It is asserted high when valid data is present on RXD [3:0].
COL
I2
80
Collision:
This signal is driven by PHY when collision is detected.
CRS
I2
79
Carrier Sense:
相關(guān)PDF資料
PDF描述
AX88190P 10/100BASE PCMCIA Fast Ethernet MAC Controller
AX88195P 10/100BASE Local CPU Bus Fast Ethernet MAC Controller
AX88196BLF Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface
AX88658AB 8-Port 10/100/1000BASE-T Ethernet Switch
AX88772_07 USB to 10/100 Fast Ethernet/HomePNA Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX88180LF 制造商:ASIX 功能描述:NON PCI MAC CONTROLLER 10/100/1000
AX88190 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:PCMCIA Fast Ethernet MAC Controller
AX88190AL 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:PCMCIA Fast Ethernet MAC Controller
AX88190P 制造商:ASIX 制造商全稱(chēng):ASIX 功能描述:10/100BASE PCMCIA Fast Ethernet MAC Controller
AX88195P 制造商:ASIX 制造商全稱(chēng):ASIX 功能描述:10/100BASE Local CPU Bus Fast Ethernet MAC Controller
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*