參數(shù)資料
型號: AX88180
廠商: ASIX Electronics Corporation
英文描述: High-Performance Non-PCI 32-bit 10/100/1000M Gigabit Ethernet Controller
中文描述: 高性能非PCI 32位10/100/1000千兆以太網(wǎng)控制器
文件頁數(shù): 17/47頁
文件大小: 420K
代理商: AX88180
AX88180
17
ASIX ELECTRONICS CORPORATION
1 = enable
0 = disable
Reserved
Watch Dog Timer Interrupt Mask
When this bit is enabled, a watch dog timer expired interrupt request set in
bit1 of Interrupt Status Register will make AX88180 to issue an interrupt to
host
1 = enable
0 = disable
RX Buffer Full Interrupt Mask
When this bit is enabled, a RX buffer full interrupt request set in bit 0 of
Interrupt Status Register will make AX88180 to issue an interrupt to host.
1 = enable
0 = disable
2
1
-
R/W
R/W
0
0
DOGIM
0
RXFULIM
R/W
0
4.3 ISR--Interrupt Status Register
Offset Address = 0xFC08 Default = 0x0000_0000
Field Name
Type
Default
31:6
-
R
All 0’s
5
PHYIG
R/W
0
Description
Reserved
PHY Interrupt Generation
If this bit is set to ‘1’, it means there is an interrupt request from PHY. AX88180
will forward this interrupt to system. Meantime driver should poll PHY and
adopt proper procedure. Write ‘1’ to this bit to clear this request status.
1 = have interrupt request
0 = no interrupt request
Receive Packet Interrupt Generation
If this bit is set to ‘1’, it means AX88180 receives a packet or (packets) from
PHY. The packet is kept in RX buffer. Write ‘1’ to this bit to clear this request
status.
1 = have received packet
0 = no received packet
Finish Transmitting Packet Interrupt
If this bit is set to ‘1’, it means AX88180 had transmitted packet to PHY. Write
‘1’ to this bit to clear this request status.
1 = finish transmission
0 = none
Reserved
Watch Dog Timer Expired Interrupt
If this bit is set to ‘1’, it means the WATCH DOG timer is expired. AX88180 will
issue an interrupt to host. Write ‘1’ to this bit to clear this request status. The
expired duration can refer to DOGTHD0 and DOGTHD1 registers.
1 = timer expired happens
0 = none
RX Buffer Full Interrupt
If this bit is set to ‘1’ it means RX buffer is full and no more packets will be
received until packets are read out. Write ‘1’ to this bit to clear this request status.
1 = RX buffer full
0 = None
4
RPIG
R/W
0
3
FTPI
R/W
0
2
1
-
R/W
R/W
0
0
WDTEI
0
RXFULI R/W
0
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