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參數(shù)資料
| 型號： | AX88180 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | High-Performance Non-PCI 32-bit 10/100/1000M Gigabit Ethernet Controller |
| 中文描述： | 高性能非PCI 32位10/100/1000千兆以太網(wǎng)控制器 |
| 文件頁數(shù)： | 27/47頁 |
| 文件大小： | 420K |
| 代理商： | AX88180 |
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AX88180
27
ASIX ELECTRONICS CORPORATION
4.31 RXINDICATOR--Receive Indicator Register
Offset Address= 0xFC90 Default = 0x0000_0000
Field
Name
Type
Default
31:1
-
R
All 0’s
0
RXSTART R/W
0
Description
Reserved
Receive Start
Driver sets this bit to start or end receive operation from RX buffer of AX88180.
1= Start read RX buffer
0= End read RX buffer
4.32 TXST--TX Status Register
Offset Address = 0xFC94 Default = 0x0000_0000
Field
Name
Type
Default
31:4
-
R
All 0’s
3
TXD3FAIL R
0
Description
Reserved
TX Descriptor3 Transmit Fail
When this bit is set 1, it means AX88180 fails in transmission of descriptor3.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor2 Transmit Fail
When this bit is set 1, it means A88180 fails in transmission of descriptor2.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor1 Transmit Fail
When this bit is set 1, it means AX88180 fails in transmission of descriptor1.
This bit will be self-cleared when driver reads TXST register.
TX Descriptor0 Transmit Fail
When this bit is set 1, it means AX88180 fails in transmission of descriptor0.
This bit will be self-cleared when driver reads TXST register.
2
TXD2FAIL R
0
1
TXD1FAIL R
0
0
TXD0FAIL R
0
4.33 MDCLKPAT--MDC Clock Pattern Register
Offset Address = 0xFCA0 Default = 0x0000_8040
Field
Name
Type
Default
31:16
-
R
All 0’s
15:8
-
R/W
0x80
7:0
MDCPAT R/W
0x40
Description
Reserved
Reserved, must set to 0x80 for normal operation
MDC Clock Divide Factor
This field defines the divided factor of host clock. AX88180 will refer to this
field and generate a low speed clock to PHY.
4.34 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter
Offset Address = 0xFCA4 Default = 0x0000_0000
Field Name
Type
Default
31:16
-
R
All 0’s Reserved
15:0
RXCHKERCNT R/W
All 0’s RX Checksum Error Counter
If the RXCHKSUM field of RX_CFG register is set to ‘1’, MAC will check the
checksum of IP, TCP or UDP packet. Whenever there is checksum error
detected, this field will be added one. The value will be rounded back to 0x0000
if it exceeds 0xFFFF.
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX88190P | 10/100BASE PCMCIA Fast Ethernet MAC Controller |
| AX88195P | 10/100BASE Local CPU Bus Fast Ethernet MAC Controller |
| AX88196BLF | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| AX88658AB | 8-Port 10/100/1000BASE-T Ethernet Switch |
| AX88772_07 | USB to 10/100 Fast Ethernet/HomePNA Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88180LF | 制造商:ASIX 功能描述:NON PCI MAC CONTROLLER 10/100/1000 |
| AX88190 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCMCIA Fast Ethernet MAC Controller |
| AX88190AL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCMCIA Fast Ethernet MAC Controller |
| AX88190P | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE PCMCIA Fast Ethernet MAC Controller |
| AX88195P | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE Local CPU Bus Fast Ethernet MAC Controller |
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