參數(shù)資料
型號(hào): AX88180
廠商: ASIX Electronics Corporation
英文描述: High-Performance Non-PCI 32-bit 10/100/1000M Gigabit Ethernet Controller
中文描述: 高性能非PCI 32位10/100/1000千兆以太網(wǎng)控制器
文件頁(yè)數(shù): 16/47頁(yè)
文件大?。?/td> 420K
代理商: AX88180
AX88180
16
ASIX ELECTRONICS CORPORATION
4.1 CMD--Command Register
Offset Address = 0xFC00 Default = 0x0000_0201
Field
Name
Type Default
31:16
-
R/W
All 0’s
15
RXVLAN
R/W
0
Description
Reserved
RX VLAN indicator
Driver enables this bit to indicate AX88180 that the received packet will
include 4 bytes VLAN tag; AX88180 will skip 4 bytes when it calculates the
checksum of IP, TCP or UDP packet.
1 = enable
0 = disable
TX VLAN indicator
Driver enables this bit to indicate AX88180 that the transmitted packet will
include 4 bytes VLAN tag; AX88180 will skip 4 bytes when it calculates the
checksum of IP, TCP or UDP packet.
1 = enable
0 = disable
Reserved
RX Function Enable
When this bit is enabled, MAC starts to receive packets.
1 = enable
0 = disable
TX Function Enable
When this bit is enabled, MAC could start to transmit packet to Ethernet.
1 = enable
0 = disable
Reserved
Interrupt Active Mode
Driver sets this bit to indicate AX88180 the interrupt of system is activated
high or low.
1: Active high
0: Active low
Reserved
WAKEUP pin polarity
Driver sets this bit to indicate AX88180 the polarity of system wake-up signal
is activated high or low.
1: Active high
0: Active low
14
TXVLAN
R/W
0
13:10
9
-
R/W
R/W
All 0’s
1
RXEN
8
TXEN
R/W
0
7
6
-
R/W
R/W
0
0
INTMOD
5:1
0
-
R/W
R/W
All 0’s
1
WAKEMOD
4.2 IMR--Interrupt Mask Register
Offset Address = 0xFC04 Default = 0x0000_0000
Field
Name
Type
Default
31:6
-
R
All 0’s
5
PHYMASK
R/W
0
Description
Reserved
PHY interrupt Mask
When this bit is enabled, an interrupt request from PHY set in bit 5 of
Interrupt Status Register will make AX88180 to issue an interrupt to host.
1 = enable
0 = disable
Packet Received Interrupt Mask
When this bit is enabled, a received interrupt request set in bit 4 of Interrupt
Status Register will make AX88180 to issue an interrupt to host.
1 = enable
0 = disable
Packet Transmitted Interrupt Mask
When this bit is enabled, a transmitted interrupt request set in bit 3 of Interrupt
Status Register will make AX88180 issue an interrupt to host.
4
PRIM
R/W
0
3
PTIM
R/W
0
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