
AX88180
5
ASIX ELECTRONICS CORPORATION
Revision History.....................................................................................................................................................................46
List of Figures
Figure 1 : AX88180 block diagram......................................................................................................................................6
Figure 2 : AX88180 pin connection diagram........................................................................................................................7
Figure 3: 32-bit mode address mapping................................................................................................................................12
Figure 4: data swap block.....................................................................................................................................................13
Figure 5: 16-bit mode memory mapping ..............................................................................................................................14
List of Tables
Table 1 : RGMII/MII Interface signals group...........................................................................................................................8
Table 2 : Host Interface signals group ......................................................................................................................................9
Table 3 : EEPROM Interface signals group............................................................................................................................10
Table 4 : Regulator signals group ...........................................................................................................................................10
Table 5 : Miscellaneous signals group....................................................................................................................................11
Table 6 : Power/Ground pins group........................................................................................................................................11
Table 7: MAC Register Mapping............................................................................................................................................15