
AX88180
18
ASIX ELECTRONICS CORPORATION
4.4 TX_CFG--TX Configuration Register
Offset Address = 0xFC10 Default = 0x0000_0040
Field Name
Type
Default Description
31:7
-
R
All 0’s
6
TXCRCAP
R/W
1
Reserved
TXCRC Auto-Append
When this bit is enabled, AX88180 will append CRC to the transmitted
packet in FCS field.
1 = enable
0 = disable
Reserved.
TX Checksum Generation
When this bit is enabled, AX88180 will append checksum to the transmitted
packet that is IP or TCP or UDP packet.
1 = enable
0 = disable
Reserved
TX Description Status
AX88180 reports which descriptor is transmitted now
Default: 2’b00
5
4
-
R/W
R/W
0
0
TXCHKSUM
3:2
1:0
-
R
R
00
00
TXDS
4.5 TX_CMD--TX Command Register
Offset Address = 0xFC14 Default = 0x0000_0000
Field
Name
Type
Default
31:16
-
R
All 0’s
15
HWI
R/W
0
Description
Reserved
Host Writes Indication
Before host begins to send a packet to TX buffer, this bit should be set. At
the end of host writes the packet, this bit should be cleared by software.
1 = Start Writing
0 = End Writing
TX Descriptor Pointer
To specify which TX descriptor to be written.
Reserved
Byte Count.
Data length is written to transmitted buffer.
14:13
TXDP
R/W
00
12
11:0
-
R/W
R/W
0
All 0’s
DATALEN
4.6 TXBS--TX Buffer Status Register
Offset Address = 0xFC18 Default = 0x0000_0000
Field Name
Type
Default Description
31:4
-
R
All 0’s
8
INTXDS
R
0
Reserved
Internal TX descriptor status.
This bit reports the TX descriptor status. When there is data to be transmitted,
this bit will be set to ‘1’ otherwise it will be ‘0’
1 = have data in TX buffer
0 = all data are transmitted to PHY
Reserved
TX Descriptor In Transmitting
These status bits indicate which descriptor is transmitting now.
00: Descriptor 0 in transmitting
01: Descriptor 1 in transmitting
10: Descriptor 2 in transmitting
11: Descriptor 3 in transmitting
TX Descriptor 3 Occupied
Driver set this bit to ‘1’ to indicate that it had used TX descriptor3. When the
7:6
5:4
-
R
00
00
TXDUSE R
3
TXD3O
R/W
0