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參數(shù)資料
| 型號： | AT43USB351M-AC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Full-speed/Low-speed USB Microcontroller with ADC and PWM |
| 中文描述： | 8-BIT, MROM, 24 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 83/101頁 |
| 文件大?。?/td> | 624K |
| 代理商： | AT43USB351M-AC |
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83
AT43USB351M
3302E–USB–7/04
Function Endpoint 0 Control and Acknowledge Register – FCAR0
Bit 7
–
DIR: Control transfer direction
It is set by the microcontroller firmware to indicate the direction of a control transfer to the USB
hardware. The FW writes to this bit location after it receives an RX SETUP interrupt. The hard-
ware uses this bit to determine the status phase of a control transfer.
0 = control write or no data stage
1 = control read
Bit 6
–
DATA END
When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last
data packet in FIFO, or that the microcontroller has processed the last data packet it expects
from the Host. This bit is used by control endpoints only together with bit 4 (TX Packet Ready)
to signal the USB hardware to go to the STATUS phase after the packet currently residing in
the FIFO is transmitted. After the hardware completes the STATUS phase it will interrupt the
microcontroller without clearing this bit.
Bit 5
–
FORCE STALL
This bit is set by the microcontroller to indicate a stalled endpoint. The hardware will send a
STALL handshake as a response to the next IN or OUT token, or whenever there is a control
transfer without a Data Stage.
The microcontroller sets this bit if it wants to force a STALL. A STALL is sent if any of the fol-
lowing condition is encountered:
1.
An unsupported request is received.
2.
The host continues to ask for data after the data is exhausted.
3.
The control transfer has no data stage.
Bit 4
–
TX PACKET READY: Transmit Packet Ready
When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a
packet of data. This bit is cleared by the hardware after the USB Host acknowledges the
packet. For ISO endpoints, this bit is cleared unconditionally after the data is sent.
This bit is used for the following operations:
1.
Control read transactions by a control endpoint.
2.
IN transactions with DATA1 PID to complete the status phase for a control endpoint,
when this bit is zero but Data End set high (bit 4).
3.
By a BULK IN or ISO IN or INT IN endpoint.
The microcontroller should write into the FIFO only if this bit is cleared. After it has completed
writing the data, it should set this bit. This data can be of zero length.
Hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Com-
plete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the
microcontroller.
Bit 3
–
STALL_SENT_ACK: Acknowledge Stall Sent Interrupt
Bit
7
6
5
4
3
2
1
0
Function
EP0 $1FDD
DIR
DATA
END
FORCE
STALL
TX
PACKET
READY
STALL_
SENT_
ACK
RX_
SETUP_
ACK
RX_OUT_
PACKET_
ACK
TX_
COMPLETE_
ACK
FCAR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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