參數(shù)資料
型號： AT43USB351M-AC
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Full-speed/Low-speed USB Microcontroller with ADC and PWM
中文描述： 8-BIT, MROM, 24 MHz, RISC MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù)： 48/101頁
文件大小： 624K
代理商： AT43USB351M-AC
48
AT43USB351M
3302E–USB–7/04
Timer/Counter1 Input Capture Register – ICR1H and ICR1L
The input capture register is a 16-bit read-only register.
When the rising or falling edge (according to the input capture edge setting - ICES1) of the sig-
nal at the input capture pin (ICP) is detected, the current value of the Timer/Counter1 is
transferred to the Input Capture Register (ICR1). At the same time, the Input Capture Flag
(ICF1) is set (one).
Since the ICR1 is a 16-bit register, a temporary register TEMP is used when ICR1 is read to
ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the
data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register.
When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP
register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read
operation.
The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main pro-
gram and also interrupt routines perform access to registers using TEMP, interrupts must be
disabled during access from the main program and from interrupt routines, if interrupts are
allowed from within interrupt routines.
Timer/Counter1 In
PWM Mode
When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A (OCR1A)
and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit, free-running, glitch-
free and phase correct PWM with outputs on the PD5 (OC1A) and OC1B pins.
Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table 16),
where it turns and counts down again to zero before the cycle is repeated. When the counter
value matches the contents of the 10 least significant bits of OCR1A or OCR1B, the
PD5(OC1A)/OC1B pins are set or cleared according to the settings of the COM1A1/COM1A0
or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register TCCR1A. Refer to Table 17
for details.
Bit
15
14
13
12
11
10
9
8
$25 ($45)
MSB
–
–
–
–
–
–
–
ICR1H
$24 ($44)
–
–
–
–
–
–
–
LSB
ICR1L
7
6
5
4
3
2
1
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 16.
Timer TOP Values and PWM Frequency
PWM Resolution
Timer TOP value
Frequency
8-bit
$00FF (255)
f
TCK1
/510
9-bit
$01FF (511)
f
TCK1
/1022
10-bit
$03FF(1023)
f
TCK1
/2046
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