參數(shù)資料
型號(hào)： AT43USB351M-AC
廠商： ATMEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： Full-speed/Low-speed USB Microcontroller with ADC and PWM
中文描述： 8-BIT, MROM, 24 MHz, RISC MICROCONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 54/101頁(yè)
文件大?。?/td> 624K
代理商： AT43USB351M-AC
54
AT43USB351M
3302E–USB–7/04
SS Pin Functionality
When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the
direction of the SS pin. If SS is configured as an output, the pin is a general output pin which
does not affect the SPI system. If SS is configured as an input, it must be held high to ensure
Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is config-
ured as master with the SS pin defined as an input, the SPI system interprets this as another
master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the
SPI system takes the following actions:
1.
The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of
the SPI becoming a slave, the MOSI and SCK pins become inputs.
2.
The SPIF flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in SREG
are set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmittal is used in master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set.
Once the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable
SPI master mode.
When the SPI is configured as a slave, the SS pin is always input. When SS is held low, the
SPI is activated and MISO becomes an output if configured so by the user. All other pins are
inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it
will not receive incoming data. Note that the SPI logic will be reset once the SS pin is brought
high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiv-
ing immediately and both data received and data sent must be considered as lost.
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Fig-
ure 18 and Figure 19.
Figure 18.
SPI Transfer Format with CPHA = 0 and DORD = 0
Note:
* Not defined but normally LSB of character just received.
*
LSB
1
2
3
4
5
6
MSB
LSB
1
2
3
4
5
6
1
2
3
4
5
6
7
8
MSB
SCK Cycle #
(For Reference)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
(From Master)
MISO
(From Slave)
SS (To Slave)
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