參數(shù)資料
型號: AT43USB351M-AC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Full-speed/Low-speed USB Microcontroller with ADC and PWM
中文描述: 8-BIT, MROM, 24 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù): 50/101頁
文件大?。?/td> 624K
代理商: AT43USB351M-AC
50
AT43USB351M
3302E–USB–7/04
(CS12..CS10 = 001 or 000), the PWM output goes active when the counter reaches the TOP
value, but the down-counting compare match is not interpreted to be reached before the next
time the counter reaches the TOP value, making a one-period PWM pulse.
Note:
X = A or B
In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from
$0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e. it is
executed when TOV1 is set provided that Timer Overflow Interrupt1 and global interrupts are
enabled. This also applies to the Timer Output Compare1 flags and interrupts.
Watchdog Timer
The Watchdog Timer is clocked from a 1 MHz clock derived from the 6 MHz on chip oscillator.
By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted,
see Table 19 for a detailed description. The WDR (Watchdog Reset) instruction resets the
Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset
period. If the reset period expires without another Watchdog reset, the AT43USB351M resets
and executes from the reset vector.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be fol-
lowed when the watchdog is disabled. Refer to the description of the Watchdog Timer Control
Register for details.
Figure 15.
Watchdog Timer
Table 18.
PWM Outputs OCR1X = $0000 or Top
COM1X1
COM1X0
OCR1X
Output OC1X
1
0
$0000
L
1
0
TOP
H
1
1
$0000
H
1
1
TOP
L
O
O
O
O
O
O
O
O
1 MHz Clock
MCU Reset
WDE
WDP2
WDP1
WDP0
Watchdog
Reset
Watchdog Prescaler
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