參數(shù)資料
型號: AT43USB351M-AC
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Full-speed/Low-speed USB Microcontroller with ADC and PWM
中文描述: 8-BIT, MROM, 24 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù): 34/101頁
文件大?。?/td> 624K
代理商: AT43USB351M-AC
34
AT43USB351M
3302E–USB–7/04
USB Interrupt Enable Register – UIER
Bit 7 – SOF IE: Enable Start of Frame Interrupt
When the SOF IE bit is set (1), the Start of Frame Interrupt is enabled.
Bit 6, 5 – Res: Reserved bits
These bits are reserved and always read as zero.
Bit 4 – FEP4 IE: Enable Function Endpoint 4 Interrupt
When the FE4 IE bit is set (1), the Function Endpoint 4 Interrupt is enabled.
Bit 3 – FEP3 IE: Function Endpoint 3 Interrupt
When the FEP3 IE bit is set (1), the Function Endpoint 3 Interrupt is enabled.
Bit 2 – FEP2 IE: Enable Endpoint 2 Interrupt
When the FE2 IE bit is set (1), the Function Endpoint 2 Interrupt is enabled.
Bit 1 – FEP1 IE: Enable Endpoint 1 Interrupt
When the FE1 IE bit is set (1), the Function Endpoint 1 Interrupt is enabled.
Bit 0 – FEP0 IE: Enable Endpoint 0 Interrupt
When the FE0 IE bit is set (1), the Function Endpoint 0 Interrupt is enabled.
Suspend/Resume Register – SPRSR
Bit 7..4 – Res: Reserved Bits
These bits are reserved and are always read as zeros.
Bit 3 – BUS INT: USB Bus Interrupt
When the USB reset separation feature is enabled (SPRSIE and SPRSMSK bits 3 are set to
1) the BUS INT bit is set when USB bus reset is detected by the USB hardware.
Bit 2 – FRWUP: Function Remote Wakeup
The USB hardware sets this bit to signal that External Interrupt 1 is detected indicating remote
wakeup. An interrupt is generated if the FRWUP IE bit of the SPRSIE register is set.
Bit 1 – RSM: Resume
The USB hardware sets this bit when a USB resume signaling is detected at any of its port
except Port 1. An interrupt is generated if the RSM IE bit of the SPRSIE register is set.
Bit 0 – GLB SUSP: Global Suspend
The USB hardware sets this bit when a USB global suspend signaling is detected. An interrupt
is generated if the GLBSUSP IE bit of the SPRSIE register is set.
Bit
7
6
5
4
3
2
1
0
$1FF3
SOF IE
FEP4 IE
FEP3 IE
FEP2 IE
FEP1 IE
FEP0 IE
UIER
Read/Write
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$1FFA
BUS INT
FRWUP
RSM
GLB SUSP
SPRSR
Read/Write
R
R
R
R
R/W
R
R
R
Initial Value
0
0
0
0
0
0
0
0
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