參數(shù)資料
型號(hào): AS4C4M4F1Q
廠商: Alliance Semiconductor Corporation
英文描述: 5V 4M×4 CMOS QuadCAS DRAM (Fast Page Mode)(5V 4M×4 CMOS QuadCAS 動(dòng)態(tài)RAM(快速頁面模式))
中文描述: 5V的4米× 4的CMOS QuadCAS的DRAM(快速頁面模式)(5V的4米× 4的CMOS QuadCAS動(dòng)態(tài)隨機(jī)存儲(chǔ)器(快速頁面模式))
文件頁數(shù): 2/16頁
文件大?。?/td> 364K
代理商: AS4C4M4F1Q
)24
$6
7
&
7
0
7
$6
7
&
7
0
7
)
4
4
$GYDQFH
#
LQIRUPDWLRQ
5
#
$//,$1&(
#
6(0,&21'8&725
','
#440633370
$
1#4257233
)XQFWLRQDO
#
GHVFULSWLRQ
The 4C4M4FOQ and AS4C4M4F1Q are high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) devices organized
as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for
use as main memory in PC, workstation, router and switch applications.
These devices feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within tha row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Four individual CAS pins allow for separate I/O operation which enables the devices to
operate in parity mode. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to
CAS assertion.
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
Normal read or write cycles refresh the row being accessed.
Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
Normal read or write cycles refresh the row being accessed.
Self-refresh cycles
The 4C4M4FOQ and AS4C4M4F1Q are available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The 4C4M4FOQ and
AS4C4M4F1Q operate with a single power supply of 5V ± 0.5V and provide TTL compatible inputs and outputs.
/RJLF
#
EORFN
#
GLDJUDP
#
IRU
#7
.
#
UHIUHVK
RAS clock
generator
R
c
4,194,304 × 4
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
V
CC
GND
A
R
Column decoder
Data
I/O
buffers
OE
RAS
CAS
WE clock
generator
WE
I/O0 to I/O3
CAS clock
generator
相關(guān)PDF資料
PDF描述
AS4C4M4FOQ 5V 4M×4 CMOS QuadCAS DRAM (Fast Page Mode)(5V 4M×4 CMOS QuadCAS 動(dòng)態(tài)RAM(快速頁面模式))
AS4LC1M16E5 3V 1M×16 CMOS DRAM (EDO)(3V 1M×16 CMOS動(dòng)態(tài)RAM(擴(kuò)展數(shù)據(jù)總線))
AS4LC1M16S1 3.3V 1M × 16 CMOS Synchronous DRAM(3.3V 1M × 16 CMOS同步動(dòng)態(tài)RAM)
AS4LC256K16EO 3.3V 256K×16 CMOS DRAM (EDO)(3.3V 256K×16 CMOS動(dòng)態(tài)RAM(擴(kuò)展數(shù)據(jù)總線))
AS4LC4M16S0 3.3V 4M × 16 CMOS Synchronous DRAM(3.3V 4M × 16 CMOS同步動(dòng)態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AS4C4M4F1Q-50JC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM
AS4C4M4F1Q-50TC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM|FAST PAGE|4MX4|CMOS|SOJ|28PIN|PLASTIC
AS4C4M4F1Q-60JC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM
AS4C4M4F1Q-60TC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM|FAST PAGE|4MX4|CMOS|TSOP|28PIN|PLASTIC
AS4C512M16D3L-12BCN 功能描述:IC SDRAM DDR3 512MX16 96FBGA COM 制造商:alliance memory, inc. 系列:- 包裝:托盤 零件狀態(tài):有效 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:DDR3L SDRAM 存儲(chǔ)容量:8G(512M x 16) 速度:800MHz 接口:并聯(lián) 電壓 - 電源:1.283 V ~ 1.45 V 工作溫度:0°C ~ 95°C(TC) 封裝/外殼:96-TFBGA 供應(yīng)商器件封裝:96-FBGA(14x9) 標(biāo)準(zhǔn)包裝:190