參數(shù)資料
型號(hào)： ARM60
廠商： Mitel Networks Corporation
英文描述： Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡(jiǎn)指令集微處理器)
中文描述： 低功耗通用32位RISC微處理器（低功耗通用32位精簡(jiǎn)指令集微處理器）
文件頁(yè)數(shù)： 92/121頁(yè)
文件大小： 1217K
代理商： ARM60
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P60ARM-B
88
7.17 Instruction Speed Summary
Due to the pipelined architecture of the CPU, instructions overlap considerably. In a typical cycle one
instruction may be using the data path while the next is being decoded and the one after that is being
fetched. For this reason the following table presents the incremental number of cycles required by an
instruction, rather than the total number of cycles for which the instruction uses part of the processor.
Elapsed time (in cycles) for a routine may be calculated from these figures which are shown in
Table 23:
ARM Instruction Speeds
. These figures assume that the instruction is actually executed. Unexecuted
instructions take one cycle.
n
is the number of words transferred.
m
is the number of cycles required by the multiply algorithm, which is determined by the contents of
Rs. Multiplication by any number between
2^(2m-3)
and
2^(2m-1)-1
takes 1S+mI
m
cycles for
1<m>16
. Multiplication by 0 or 1 takes 1S+1I cycles, and multiplication by any number greater than
or equal to 2^(29) takes 1S+16I cycles. The maximum time for any multiply is thus 1S+16I cycles.
b
is the number of cycles spent in the coprocessor busy-wait loop.
If the condition is not met all instructions take one S cycle. The cycle types (N, S, I and C) are deTned in
Chapter 5.0 Memory Interface
.
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
1
pc+8
1
0
(pc+8)
0
1
0
pc+12
Table 22: Unexecuted Instruction Cycle Operations
Instruction
Data Processing
Cycle count
Additional
1S
+ 1I for SHIFT(Rs)
+ 1I + 1N if R15 written
MSR, MRS
LDR
STR
LDM
STM
SWP
B,BL
SWI, trap
MUL,MLA
CDP
LDC,STC
MRC
MCR
1S
1S
+ 1N
2N
+ 1N
+ 2N
+ 2N
+ 1N
+ 1N
+
1I
+ 1S + 1N if R15 loaded
nS
+
1I
+ 1S + 1N if R15 loaded
(n-1)S
1S
2S
2S
1S
1S
+
1I
+
+
mI
bI
bI
bI
(n-1)S
+ 2N
+
1S
1S
+
+
+ 1C
+ 1C
(b+1)I
Table 23: ARM Instruction Speeds
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