參數(shù)資料
型號(hào): ARM60
廠商: Mitel Networks Corporation
英文描述: Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡指令集微處理器)
中文描述: 低功耗通用32位RISC微處理器(低功耗通用32位精簡指令集微處理器)
文件頁數(shù): 113/121頁
文件大?。?/td> 1217K
代理商: ARM60
AC Parameters
109
Figure 45: Exception Timing
Note:
Tirs, Trs guarantee recognition of the interrupt (or reset) source by the corresponding clock edge.
Tirm, Trh guarantee non-recognition by that clock edge. These inputs may be applied fully
asynchronously where the exact cycle of recognition is unimportant.
Figure 46: Clock Timing
Note:
The ARM core is not clocked by the HIGH phase of
cycles shown,
nMREQ
and
change once, during the second HIGH phase of
internal clock from which the core times all its activity. This signal is included to show how the high
phase of the external
MCLK
has been removed from the internal core clock.
MCLK
enveloped by
nWAIT
. Thus, during the
MCLK
, and
SEQ
change once, during the first LOW phase of
MCLK
A[31:0]
. For reference, ph2 is shown. This is the
MCLK
ABORT
nRESET
nFIQ, nIRQ
T
abts
T
abth
T
rs
T
rh
T
irs
T
irm
MCLK
nWAIT
ph2
nMREQ/
SEQ
A[31:0]
T
clkl
T
clkh
T
ws
T
wh
T
msd
T
addr
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