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參數(shù)資料
| 型號(hào)： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡指令集微處理器） |
| 文件頁數(shù)： | 16/121頁 |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
12
Figure 4:
Format of the Program Status Registers (PSRs)
The format of the Program Status Registers is shown in
(PSRs)
. The N, Z, C and V bits are the
changed as a result of arithmetic and logical operations in the processor and may be tested by all
instructions to determine if the instruction is to be executed.
Figure 4: Format of the Program Status Registers
. The condition code flags in the CPSR may be
condition code flags
The I and F bits are the
disables FIQ interrupts when it is set. The M0, M1, M2, M3 and M4 bits (M[4:0]) are the
determine the mode in which the processor operates. The interpretation of the mode bits is shown in
2: The Mode Bits
. Not all combinations of the mode bits define a valid processor mode. Only those explicitly
described shall be used.
interrupt disable bits.
The I bit disables IRQ interrupts when it is set and the F bit
mode bits
, and these
Table
The bottom 28 bits of a PSR (incorporating I, F and M[4:0]) are known collectively as the
control bits will change when an exception arises and in addition can be manipulated by software when the
processor is in a privileged mode. Unused bits in the PSRs are reserved and their state shall be preserved
when changing the flag or control bits. Programs shall not rely on specific values from the reserved bits
when checking the PSR status, since they may read as one or zero in future processors.
control bits
. The
M[4:0]
Mode
Accessible register set
10000
User
PC, R14..R0
CPSR
10001
FIQ
PC, R14_fiq..R8_fiq, R7..R0
CPSR, SPSR_fiq
10010
IRQ
PC, R14_irq..R13_irq, R12..R0
CPSR, SPSR_irq
10011
Supervisor
PC, R14_svc..R13_svc, R12..R0
CPSR, SPSR_svc
10111
Abort
PC, R14_abt..R13_abt, R12..R0
CPSR, SPSR_abt
11011
Undefined
PC, R14_und..R13_und, R12..R0
CPSR, SPSR_und
Table 2: The Mode Bits
0
1
2
3
4
5
6
7
8
27
28
29
30
31
M0
M1
M2
M3
M4
.
F
I
V
C
Z
N
Overflow
Carry / Borrow / Extend
Zero
Negative / Less Than
Mode bits
FIQ disable
IRQ disable
.
.
.
flags
control
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