參數(shù)資料
型號(hào)： ARM60
廠商： Mitel Networks Corporation
英文描述： Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡(jiǎn)指令集微處理器)
中文描述： 低功耗通用32位RISC微處理器（低功耗通用32位精簡(jiǎn)指令集微處理器）
文件頁數(shù)： 27/121頁
文件大?。?/td> 1217K
代理商： ARM60
Instruction Set - Data processing
23
4.4 Data
processing
The instruction is only executed if the condition is true, defined at the beginning of this chapter. The
instruction encoding is shown in
Figure 8: Data Processing Instructions
.
The instruction produces a result by performing a specified arithmetic or logical operation on one or two
operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or
a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction. The condition
codes in the CPSR may be preserved or updated as a result of this instruction, according to the value of the
S bit in the instruction. Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are
used only to perform tests and to set the condition codes on the result and always have the S bit set. The
instructions and their effects are listed in
Table 4: ARM Data Processing Instructions
.
Figure 8: Data Processing Instructions
Cond
00
I
OpCode
Rn
Rd
Operand 2
0
11
12
15
16
19
20
21
24
25
26
27
28
31
Destination register
1st operand register
Set condition codes
1 = set condition codes
Operation Code
0000 = AND - Rd:= Op1 AND Op2
0001 = EOR - Rd:= Op1 EOR Op2
0010 = SUB - Rd:= Op1 - Op2
0011 = RSB - Rd:= Op2 - Op1
0100 = ADD - Rd:= Op1 + Op2
0101 = ADC - Rd:= Op1 + Op2 + C
0110 = SBC - Rd:= Op1 - Op2 + C
0111 = RSC - Rd:= Op2 - Op1 + C
1000 = TST - set condition codes on Op1 AND Op2
1001 = TEQ - set condition codes on Op1 EOR Op2
1010 = CMP - set condition codes on Op1 - Op2
1100 = ORR - Rd:= Op1 OR Op2
1101 = MOV - Rd:= Op2
1110 = BIC - Rd:= Op1 AND NOT Op2
1111 = MVN - Rd:= NOT Op2
Immediate Operand
0 = operand 2 is a register
11
1 = operand 2 is an immediate value
8
7
Shift
Rm
Rotate
S
Unsigned 8 bit immediate value
2nd operand register
shift applied to Rm
shift applied to Imm
Imm
Condition field
11
0
0
3
4
- 1
- 1
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