參數(shù)資料
型號(hào): AMIS-53050
英文描述: Frequency Agile Transceiver
中文描述: 捷變頻收發(fā)器
文件頁(yè)數(shù): 97/107頁(yè)
文件大?。?/td> 2576K
代理商: AMIS-53050
AMIS-53050
Frequency Agile Transceiver
Data Sheet
97
AMI Semiconductor
– Jan. 07, M-20639-002
www.amis.com
, LOP Enabled
7.2.9.3.
Use ID Enabled, CRC Enabled
Table 108: Receive
Parameter
ID
CRC
LOP
CRC
invalid
CRC valid
Table 109: Transmit
Parameter
Action
Data interface immediately ready after ID detected
As soon as the ID is validated, the CRC starts processing the data
The LOP is received
The rest of the received data packet is buffered into memory
The last byte is the CRC and if invalid, the receive
r waits for a command from the external host controller, or if the receiver
came from idle it will return to receive
Receiver returns to previous state and an interrupt is issued to the external controller
The data interface is started and the data is sent to the controller, except for the C
RC
Action
If buffered transmit is sele
AMIS-53050 as m
Transmit command (or end of TX data transfer) immediately powers the transmitter on
Transm
preamble (length of preamble as specified)
its
Transmits the SOF and the ID
The CR
egins
C b
processing the data with the ID
Starts data interface and uses a synchronous clock to clock in the TX data (Master only)
or clock
ata ou
s d
t of memory (buffered TX)
The firs
te is defined to be the LOP of the packet
t by
At the end of the
packet, the data stops and the CRC value is
th
acket is
After e p
transmitted, the transmitter waits for a command f
Buffered transmit
a into memory with
cted, the AMIS-53050 will open the data interface and transfer all TX dat
aster or external controller as master
Transmit
ID
CRC
LOP
CRC byte
sent
rom the external host controller
Figure 51: Data Interface Protocol (ID, LOP and CRC)
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