參數(shù)資料
型號： AMIS-53050
英文描述： Frequency Agile Transceiver
中文描述： 捷變頻收發(fā)器
文件頁數(shù)： 104/107頁
文件大?。?/td> 2576K
代理商： AMIS-53050
AMIS-53050
Frequency Agile Transceiver
Data Sheet
104
AMI Semiconductor
– Jan. 07, M-20639-002
www.amis.com
10.0 Register Definition
Table 118 contains the addresses for all of the internal registers. Once the EE has been written, the POR states for the registers
become the data last written. Should the CheckSum fail, all registers will return to the POR state shown and an error flag will be written
to a status register.
Table 119: Register List
Address
R/W
Hex
Dec
R/W
0x00
0
Command
Instruction register
R/W
0x01
1
Status/Flag1
Part status, flags
R/W
0x02
2
Status/Flag2
Part status, flags
R/W
0x03
3
Chip address 1
Upper 8 bits of chip address
R/W
0x04
4
Chip address 0
Lower 8 bits of chip address
R/W
0x05
5
RF divider
Integer portion of RF frequency
R/W
0x06
6
RF frequency 2
Upper 8 bits of RF fraction
R/W
0x07
7
RF frequency 1
Center 8 bits of RF fraction
R/W
0x08
8
RF frequency 0
Lower 8 bits of RF fraction
R/W
0x09
9
Peak deviation 1
Upper 8 bits of FM deviation
R/W
0X0A
10
Peak deviation 0
Lower 8 bits of FM deviation
R/W
0x0B
11
Data rate / format
Set discrete data rate and encoding option
General options for interface, POR state,
etc.
General options for interface, POR state,
etc.
R/W
0x0E
14
RX config
Receiver options
R/W
0x0F
15
TX config
Transmit options
R/W
0x10
16
Idle config
Idle mode options
R/W
0x11
17
Sniff config
Sniff mode options
R/W
0x12
18
Sniff interval
Interval between Sniff cycles
R/W
0x13
19
Energy dwell time
Length of time to dwell in sniff mode
Number of bit times to wait for code
after energy detect
Threshold for wake on RSSI, sniff
and CCA
R/W
0x16
22
Burst config
Burst transmit options
R/W
0x17
23
Burst interval
Interval timer for burst transmit
R/W
0x18
24
Output power
Output power
R/W
0x19
25
Start of frame
Byte used for burst transmit/CDR wake up
Length of CW, or ‘10’
repeated in Burst/TX (BT’s)
R/W
0x1B
27
HK config
Housekeeping options register
R/W
0x1C
28
HK interval
Interval timer for Housekeeping
Energy threshold for AM DAC mode
data slice
R/W
0x1E
30
Filter/slice
AM/RSSI filter setting and AM slice mode
R/W
0x1F
31
CDR options A
Clock and data recovery options A
R/W
0x20
32
CDR options B
Clock and data recovery options B
R/W
0x21
33
Crystal trim
Crystal trim
R/W
0x22
34
LNA trim
LNA input and output matching trim
R/W
0x23
35
Quick Start trim
Quick Start oscillator trim
Register Name
Description
POR State
EE
Section
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
X
X
X
X
X
X
X
X
X
6.2
6.4.5.1
6.4.5.2
7.1.1
7.1.2
6.4.1.1
6.4.1.2
6.4.1.3
6.4.1.4
6.4.1.5
6.4.1.6
7.1.3
R/W
0x0C
12
General options A
0000_0000
X
7.1.4
R/W
0x0D
13
General options B
0000_0000
X
7.1.5
0000_0000
0000_0000
1011_0100
0000_1010
0000_0000
X
X
X
X
X
X
6.5.1.1
6.6.1
6.7.1
6.7.2.1
6.7.2.2
6.7.2.3
R/W
0x14
20
Code dwell timer
0000_0000
X
6.5.1.5
R/W
0x15
21
Energy threshold
0000_0000
X
6.5.1.2
0000_0000
0001_1000
0001_0000
0001_0000
X
X
X
X
6.7.3
6.7.3.1
6.6.2
7.1.6
R/W
0x1A
26
Preamble length
0001_0000
X
6.6.3
X
X
6.7.4.1
6.7.4.2
R/W
0x1D
29
Slice threshold
X
6.5.1.4
1000_0000
0000_0000
0000_0000
0000_0000
X
X
X
X
X
X
6.5.1.4
6.5.1.5
6.5.1.5
6.10.1.1
6.10.1.2
6.10.1.3
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