參數資料
型號: AMIS-53050
英文描述: Frequency Agile Transceiver
中文描述: 捷變頻收發(fā)器
文件頁數: 37/107頁
文件大?。?/td> 2576K
代理商: AMIS-53050
AMIS-53050
Frequency Agile Transceiver
Data Sheet
Figure 26: Sequential Control Register Read/Write Using the 3-Wire Interface
F
identical
eight bits of data tr
transferred. This ta
fractiona
The SSN
the next
eight
diagr
t for a
or sequential re
/write op
correspond
ansferred
sk is most useful
registers 03-
control data transfer. The format of the instruction and address is
r location to read or write. The first
internally incremented after each data byte is
bles spanning over multiple address locations, such as the
writing to or reading from varia
for
word (
must b
bits as
at the
and not
read/write in order for the slave SPI controller to correctly interpret
6.1.4. I
2
C Interface
T
device.
I
2
C
e for the AMIS-53050 is
with the AMIS-53050 as the slave
defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is
elected. Following the start condition, the AMIS-53050 monitors the SDA bus checking the device type identifier being transmitted.
s
Upon receiving its device address, the AMIS-53050 outputs an acknowledge signal on the SDA line. Depending on the state of the R/W
bit, the AMIS-53050 will select a read or write operation.
igure 26 is a
am f
single read
ads or writes for 3-wire
eration, with the address corresponding to the first registe
to the address selected. The address is
to tha
05).
l PLL
line
e de-asserted
a command
completion of a sequential
data.
he
interfac
compatible with the Philip Semiconductor I
2
C standard,
6.1.4.1.
I2C Device Addressing
A control byte is the first byte received following the start condition from the Master device. The control byte consists of 7-bits for the
device address, and 1-bit for a read or write command. For the AMIS-53050, the device address is ‘0110100’ binary. The last bit of the
control byte
37
AMI Semiconductor
– Jan. 07, M-20639-002
www.amis.com
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