參數(shù)資料
型號(hào): AMIS-53050
英文描述: Frequency Agile Transceiver
中文描述: 捷變頻收發(fā)器
文件頁(yè)數(shù): 31/107頁(yè)
文件大?。?/td> 2576K
代理商: AMIS-53050
AMIS-53050
Frequency Agile Transceiver
Data Sheet
Figure 20: Minimum Design Layout Suggestion
6.0 Us
er’s Guide
This user’s guide divides the description of the control registers into distinct functional areas; command register flow diagrams,
ata/control interfaces, and burst transmission, respectively.
frequency generation, receiver, transmitter, idle, d
Control Se
1: Contr
6.1
rial Interface Bus Description
Table 1
ol Interface Physical Configuration
Clock
Data
Power
Interface
AMIS-
53050
Version
Pin
Source
Output
Input
SSN
AMIS-53050
RX
Standby
-001
SCLK
Master
SDATA
SDATA
RegC
Slave only
Low
Med.
I
2
C
-002
SCLK
Master
SDATA
SDATA
NU
Slave only
Med.
Low
3-Wire
-002
SCLK
Master
SDATA
SDATA
Select
Slave only
Med.
Low
Note: The I
2
C control bus interface can be used with either the –001 or the –002 version of the AMIS-53050, but the SPI can only be used with the –002 version. The
versions are different due to the receiver power requirements as shown.
The AMIS-53050 employs two different control interfaces. Communication with the AMIS-53050 control registers is through either a
3-wire bus or a 2-wire I
C compatible bus, respectively. The state of the control bus is detected by the device at the onset of
communication with the host controller, and is valid as long as power remains applied to the part. In this case, the transceiver is always
a slave device.
6.1.1. Control Interface Protocol
The AMIS-53050 control interface allows an external host controller to write instructions to the registers. The external controller can
also read the register values. The control interface can be configured as either a 2-wire I
2
C interface bus or a 3-wire serial interface
(slave mode operation).
31
AMI Semiconductor
– Jan. 07, M-20639-002
www.amis.com
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